Issues for Construction of 300-mm Fab

• Published in: Journal of construction engineering and management Vol. 126; no. 6; pp. 451 - 457
• Main Authors: Chasey, Allan D, Merchant, Saloni
• Format: Journal Article
• Language: English
• Published: Reston, VA American Society of Civil Engineers 01-12-2000
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; TECHNICAL PAPERS; Production management; Microelectronic fabrication; Circuit design; Electronics industry; Integrated circuit; Cost analysis; Wafer
• ISSN: 0733-9364; 1943-7862
• DOI: 10.1061/(ASCE)0733-9364(2000)126:6(451)

The cost of constructing and tooling a semiconductor facility, which is currently more than $1 billion, is expected to double by the year 2000, driving semiconductor chip manufacturers to adopt strategies to minimize cost to maximize the return on investment. What seems to be an inevitable transition to the larger, 300-mm wafer will have a widespread impact with massive economic implications. Preliminary tool designs and process approach standards suggest increased automation of material handling and storage systems, increases in utility consumption, tool height and weight requirements, and schedule compression. Moreover, the contamination sensitivity of the 300-mm wafer might require modification in the fab construction protocol, which in turn could affect labor productivity. Such changes will have a significant impact on construction methods, materials, and management techniques. This paper discusses the key areas in which research is necessary, focusing mainly on issues that have the maximum impact on design and construction of 300-mm fabs. While not providing solutions, this paper is intended to act as a catalyst for further research as 300-mm technology moves closer to becoming a reality.