Dynamically Trading Frequency for Complexity in a GALS Microprocessor

• Published in: 37th International Symposium on Microarchitecture (MICRO-37'04) pp. 157 - 168
• Main Authors: Dropsho, Steven, Semeraro, Greg, Albonesi, David H., Magklis, Grigorios, Scott, Michael L.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 04-12-2004; IEEE
• Series: ACM Conferences
• Subjects: Application software; Applied sciences; Clocks; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Frequency conversion; General and reference; General and reference > Cross-computing tools and techniques; General and reference > Cross-computing tools and techniques > Performance; Hardware; Hardware > Hardware validation; Indium tin oxide; Integrated circuits; Integrated circuits by function (including memories and processors); Microprocessors; Parallel processing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Throughput; Timing; Voltage; Performance evaluation; Globally asynchronous locally synchronous; Very high frequency; Cache memory; Programming environment; Energy economy; Adaptive processor; Frequency domain method; On-line systems; Clock; Queueing system; Integrated circuit; Parallelism; Branch prediction; Microprocessor; Miniaturization; Queue
• ISBN: 0769521266; 9780769521268
• ISSN: 1072-4451
• DOI: 10.1109/MICRO.2004.18

Microprocessors are traditionally designed to provide "best overall" performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by "downsizing" hardware resources that are underutilized by the current application phase. Others have proposed a different energy-saving approach: dividing the processor into domains and dynamically changing the clock frequency and voltage within each domain during phases when the full domain frequency is not required. What has not been studied to date is how to exploit the adaptive nature of these approaches to improve performance rather than to save energy. In this paper, we describe an adaptive globally asynchronous, locally synchronous (GALS) microprocessor with a fixed global voltage and four independently clocked domains. Each domain is streamlined with modest hardware structures for very high clock frequency. Key structures can then be upsized on demand to exploit more distant parallelism, improve branch prediction, or increase cache capacity. Although doing so requires decreasing the associated domain frequency, other domain frequencies are unaffected. Our approach, therefore, is to maximize the throughput of each domain by finding the proper balance between the number of clock periods, and the clock frequency, for each application phase. To achieve this objective, we use novel hardware-based control techniques that accurately and efficiently capture the performance of all possible cache and queue configurations within a single interval, without having to resort to exhaustive online exploration or expensive offline profiling. Measuring across a broad suite of application benchmarks, we find that configuring our adaptive GALS processor just once per application yields 17.6% better performance, on average, than that of the "best overall" fully synchronous design. By adapting automatically to application phases, we can increase this advantage to more than 20%.