(Invited) Cross-Layer Resilience: Challenges, Insights, and the Road Ahead

• Published in: 2019 56th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 4
• Main Authors: Cheng, Eric, Mueller-Gritschneder, Daniel, Abraham, Jacob, Bose, Pradip, Buyuktosunoglu, Alper, Chen, Deming, Cho, Hyungmin, Li, Yanjing, Sharif, Uzair, Skadron, Kevin, Stan, Mircea, Schlichtmann, Ulf, Mitra, Subhasish
• Format: Conference Proceeding
• Language: English
• Published: ACM 01-06-2019
• Subjects: Aging; Cross-layer resilience; Fault tolerance; Hardware; Integrated circuit modeling; Manufacturing; Program processors; reliability; Resilience
• DOI: 10.1145/3316781.3323474

Resilience to errors in the underlying hardware is a key design objective for a large class of computing systems, from embedded systems all the way to the cloud. Sources of hardware errors include radiation, circuit aging, variability induced by manufacturing and operating conditions, manufacturing test escapes, and early-life failures. Many publications have suggested that cross-layer resilience, where multiple error resilience techniques from different layers of the system stack cooperate to achieve cost-effective resilience, is essential for designing cost-effective resilient digital systems. This paper presents a comprehensive overview of cross-layer resilience by addressing fundamental cross-layer resilience questions, by summarizing insights derived from recent advances in cross-layer resilience research, and by discussing future cross-layer resilience challenges. CCS CONCEPTS * General and reference \rightarrow Reliability; * Hardware \rightarrow Fault tolerance; * Computer systems organization \rightarrow Reliability