DHTM: Durable Hardware Transactional Memory

• Published in: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) pp. 452 - 465
• Main Authors: Joshi, Arpit, Nagarajan, Vijay, Cintra, Marcelo, Viglas, Stratis
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2018
• Subjects: ACID transactions; Coherence; Complexity theory; Computer crashes; crash consistency; Hardware; hardware transactional memory; logging; non volatile memory; Nonvolatile memory; persistent memory; Protocols; Software
• DOI: 10.1109/ISCA.2018.00045
• EISSN: 2575-713X

The emergence of byte-addressable persistent (non-volatile) memory provides a low latency and high bandwidth path to durability. However, programmers need guarantees on what will remain in persistent memory in the event of a system crash. A widely accepted model for crash consistent programming is ACID transactions, in which updates within a transaction are made visible as well as durable in an atomic manner. However, existing software based proposals suffer from significant performance overheads. In this paper, we support both atomic visibility and durability in hardware. We propose DHTM (durable hardware transactional memory) that leverages a commercial HTM to provide atomic visibility and extends it with hardware support for redo logging to provide atomic durability. Furthermore, we leverage the same logging infrastructure to extend the supported transaction size (from being L1-limited to LLC-limited) with only minor changes to the coherence protocol. Our evaluation shows that DHTM outperforms the state-of-the-art by an average of 21% to 25% on TATP, TPC-C and a set of microbenchmarks. We believe DHTM is the first complete and practical hardware based solution for ACID transactions that has the potential to significantly ease the burden of crash consistent programming.