3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems

• Published in: 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) pp. 1 - 10
• Main Authors: Chen Pan, Mimi Xie, Jingtong Hu, Yiran Chen, Chengmo Yang
• Format: Conference Proceeding
• Language: English
• Published: ACM 01-10-2014
• Subjects: Computer architecture; Nonvolatile memory; Optimal scheduling; Phase change materials; Resistance; Schedules; Scheduling
• DOI: 10.1145/2656075.2656076

Multi-level Cell (MLC) Phase Change Memory (PCM) has many attractive features to be used as main memory for embedded systems. These features include low power, high density, and better scalability. However, there are also two drawbacks in MLC PCM, namely, limited write endurance and expensive write operation, that need to be overcome in order to practically adopt MLC PCM as main memory. In MLC PCM, two different types of write operations with very diverse data retention time are allowed. The first type maintains data for years, but takes longer time to write and hurts the endurance. The second type maintains data for a short period, but takes shorter time to write and hurts the endurance less. By observing that many data written to main memory are temporary and do not need to last long during the execution of a program, in this paper, we propose novel task scheduling and write operation selection algorithms to improve MLC PCM endurance and program efficiency. An Integer Linear Programming (ILP) formulation is first proposed to obtain optimal results. Since ILP takes exponential time to solve, we also propose a Multi-Write Mode Aware Scheduling (MMAS) heuristic to achieve near-optimal solution in polynomial time. The experimental results show that the proposed techniques can greatly improve the lifetime of MLC PCM as well as the efficiency of the program.