Efficient Memory Integrity Verification and Encryption for Secure Processors

• Published in: International Symposium on Microarchitecture: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture; 03-05 Dec. 2003 p. 339
• Main Authors: Suh, G. Edward, Clarke, Dwaine, Gassend, Blaise, Dijk, Marten van, Devadas, Srinivas
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 03-12-2003
• Series: ACM Conferences
• Subjects: Hardware > Integrated circuits > Semiconductor memory; Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
• ISBN: 076952043X; 9780769520438
• DOI: 10.5555/956417.956575

Secure processors enable new sets of applications suchas commercial grid computing, software copy-protection,and secure mobile agents by providing security from bothphysical and software attacks. This paper proposes newhardware mechanisms for memory integrity verification andencryption, which are two key primitives required in single-chipsecure processors. The integrity verification mechanismoffers significant performance advantages over existingones when the checks are infrequent as in grid computingapplications. The encryption mechanism improves theperformance in all cases.