Using a configurable processor generator for computer architecture prototyping

• Published in: 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 358 - 369
• Main Authors: Solomatnikov, Alex, Firoozshahian, Amin, Shacham, Ofer, Asgar, Zain, Wachs, Megan, Qadeer, Wajahat, Richardson, Stephen, Horowitz, Mark
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 12-12-2009; IEEE
• Series: ACM Conferences
• Subjects: Application software; Buildings; Computer architecture; computer architecture prototyping; Computer systems organization > Architectures > Parallel architectures > Multiple instruction, multiple data; configurable/extensible processor generator; General and reference > Cross-computing tools and techniques > Design; Hardware; Hardware > Very large scale integration design; Hardware > Very large scale integration design > VLSI system specification and constraints; memory system architecture; Prototypes; Reconfigurable architecture; Runtime; Software libraries; Software prototyping; Software tools; Streaming media; VLSI design; VLSI design; reconfigurable architecture; memory system architecture; configurable/extensible processor generator; computer architecture prototyping
• ISBN: 9781605587981; 1605587982
• ISSN: 1072-4451
• DOI: 10.1145/1669112.1669159

Building hardware prototypes for computer architecture research is challenging. Unfortunately, development of the required software tools (compilers, debuggers, runtime) is even more challenging, which means these systems rarely run real applications. To overcome this issue, when developing our prototype platform, we used the Tensilica processor generator to produce a customized processor and corresponding software tools and libraries. While this base processor was very different from the streamlined custom processor we initially imagined, it allowed us to focus on our main objective---the design of a reconfigurable CMP memory system---and to successfully tape out an 8-core CMP chip with only a small group of designers. One person was able to handle processor configuration and hardware generation, support of a complete software tool chain, as well as developing the custom runtime software to support three different programming models. Having a sophisticated software tool chain not only allowed us to run more applications on our machine, it once again pointed out the need to use optimized code to get an accurate evaluation of architectural features.