Transforming VHDL descriptions into formal component-based models

In this work, we investigate a transformation of VHDL descriptions into equivalent formal models. The targeted equivalence is at the level of the functional behavior. That is, we aim at producing formal models that have the same functional simulation behavior as the original VHDL implementation. We...

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Bibliographic Details

Published in:	2016 International Symposium on Rapid System Prototyping (RSP) pp. 1 - 8
Main Authors:	Nouri, Ayoub, Ben Atitallah, Rahma, Molnos, Anca, Fabre, Christian, Heitzmann, Frédéric, Debicki, Olivier
Format:	Conference Proceeding
Language:	English
Published:	ACM 01-10-2016
Subjects:	Acceleration Analytical models Hardware Integrated circuit modeling Kernel Registers Semantics
Online Access:	Get full text
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