Search Results - "van der Meijs, N.P."
-
1
Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors
Published in 2009 IEEE Custom Integrated Circuits Conference (01-09-2009)“…The on-going reduction of the on-chip feature size goes together with an increase of process variability. While the manufacturer is expected to improve the…”
Get full text
Conference Proceeding
-
2
The hybrid element method for EMC problems in VLSI circuits
Published in 3rd International Conference on Computation in Electromagnetics (CEM 96) (1996)“…One of the important EMC problems in integrated circuits (ICs) is crosstalk. This phenomenon can be an especially troublesome problem in high-density layouts,…”
Get full text
Conference Proceeding -
3
A Radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system
Published in 2009 IEEE International SOC Conference (SOCC) (01-09-2009)“…This paper presents a novel parallel pipeline FFT processor especially tailored for Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) Ultra…”
Get full text
Conference Proceeding -
4
Statistically aware buffer planning
Published in Proceedings Design, Automation and Test in Europe Conference and Exhibition (2004)“…In this paper, we will develop an analytic approach to estimate the statistical properties (mean and variance) of the performance of a uniformly buffered…”
Get full text
Conference Proceeding -
5
Coherent interconnect/substrate modeling using SPACE - an experimental study
Published in ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 (2003)“…The functionality of modern ICs increasingly suffers from substrate noise. Digital transistors switching at high frequencies are known to induce substrate…”
Get full text
Conference Proceeding -
6
Analytic model for area and power constrained optimal repeater insertion
Published in ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) (2003)“…We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a…”
Get full text
Conference Proceeding -
7
Sensitivity computation of interconnect capacitances with respect to geometric parameters
Published in 2008 IEEE-EPEP Electrical Performance of Electronic Packaging (01-10-2008)“…This paper presents an algorithm that enables an extension of standard 3d capacitance extraction to take into account the effects of small dimensional…”
Get full text
Conference Proceeding -
8
Capacitance Sensitivity Calculation for Interconnects by Adjoint Field Technique
Published in 2008 12th IEEE Workshop on Signal Propagation on Interconnects (01-05-2008)“…This paper presents a new, efficient algorithm for capacitance sensitivity calculation w.r.t. geometric variations due to process imperfection of…”
Get full text
Conference Proceeding -
9
Simultaneous analytic area and power optimization for repeater insertion
Published in ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) (2003)“…We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a…”
Get full text
Conference Proceeding -
10
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits
Published in Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors (1995)“…In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called…”
Get full text
Conference Proceeding -
11
Layout Extraction of 3D Models for Interconnect and Substrate Parasitics
Published in ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference (01-09-1995)“…In modern VLSI design it is of vital importance to know the influence of parasitics on the behaviour of the circuit. The most important parasitics are the…”
Get full text
Conference Proceeding -
12
An efficient method for substrate impedance extraction
Published in Research in Microelectronics and Electronics, 2005 PhD (2005)“…A technique for extraction of substrate impedance from low frequency to high frequency has been presented. The Complex Green’s function is also applied as a…”
Get full text
Conference Proceeding -
13
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
Published in Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) (1993)“…For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we…”
Get full text
Conference Proceeding -
14
Delayed frontal solution for finite-element based resistance extraction
Published in 32nd Design Automation Conference (01-01-1995)“…To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with…”
Get full text
Conference Proceeding -
15
-
16
Reduced RC models for IC interconnections with coupling capacitances
Published in [1992] Proceedings The European Conference on Design Automation (1992)“…The transmission behavior of interconnections in integrated circuits is often determined by their distributed RC effects. The authors present a modeling…”
Get full text
Conference Proceeding -
17
Space-efficient extraction algorithms
Published in [1992] Proceedings The European Conference on Design Automation (1992)“…A description is given of how the authors limited the space complexity of a layout to circuit extractor by: a combination of the scanline technique with the…”
Get full text
Conference Proceeding -
18
Virtual screening: a step towards a sparse partial inductance matrix
Published in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) (1999)“…We extend the partial inductance concept by replacing the magnetic interaction between open filaments i and j by that between filament j and a (finite) closed…”
Get full text
Conference Proceeding Journal Article -
19
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling
Published in IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002 (2002)“…In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately…”
Get full text
Conference Proceeding -
20
Extraction of circuit models for substrate cross-talk
Published in Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) (1995)“…An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. The paper…”
Get full text
Conference Proceeding
