Search Results - "de Marneffe, J.F."

Integrating ENSEMBLE™ PMD low- k at the PMD level of CMOS logic circuits by Demuynck, S., de Marneffe, J.F., Le, Q.T., Vos, I., Devriendt, K., Van Hove, M., Waeterloos, J., Howard, K., Popa, P., Wilson, L., Mills, L.

“…In this paper, we report on the integration of a spin-on low- k material (ENSEMBLE™ PMD) at the pre-metal dielectric (PMD) level of CMOS logic circuits…”
Get full text

Thermally activated flux motion in YBa2(Cu1−xZnx)3O7−δ epitaxial thin films: influence of magnetic field and Zn doping by Schroeder, J., Ye, M., de Marneffe, J.F., Mehbod, M., Deltour, R., Jansen, A.G.M., Wyder, P.

Get full text

Thermally activated flux motion in YBa 2(Cu 1− xZn x) 3O 7−δ epitaxial thin films: influence of magnetic field and Zn doping by Schroeder, J., Ye, M., de Marneffe, J.F., Mehbod, M., Deltour, R., Jansen, A.G.M., Wyder, P.

“…High quality c-axis oriented epitaxial YBa 2(Cu 1− x ) 3O 7− δ ( x = 0, 0.02, 0.04) thin films were deposited by DC magnetron sputtering on MgO (100)…”
Get full text

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits by Witters, L., Collaert, N., Nackaerts, A., Demand, M., Demuynek, S., Delvaux, C., Lauwers, A., Baerts, C., Beckx, S., Bouilart, W., Brus, S., Degroote, B., de Marneffe, J.F., Dixit, A., De Meyer, K., Ercken, M., Goodwin, M., Hendrickx, E., Heylen, N., Jaenen, P., Laidler, D., Leray, P., Locorotondo, S., Maenhoudt, M., Moclants, M., Pollentier, I., Ronse, K., Rooyackers, R., Van Aelst, J., Vandenberghe, G., Vandeweyer, T., Vanhaelemeersch, S., Van Hove, M., Van Olmen, J., Verhaegen, S., Versluijs, J., Vrancken, C., Wiaux, V., Willems, P., Wouters, J., Jurezak, M., Biesemans, S.

“…We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several…”
Get full text

Widening of FUSI RTP Process Window by Spike Anneal by Lauwers, A., Mertens, S., Absil, P., Chiarella, T., Hoffmann, T., Kubicek, S., de Marneffe, J.F., Brijs, A.B., Vrancken, C., Biesemans, S., Kittl, J., Verheyden, K., Vanormelingen, K., Granneman, E.

“…The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket…”
Get full text

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON by Yu, H.Y., Singanamalla, R., Opsomer, K., Augendre, E., Simoen, E., Kittl, J.A., Kubicek, S., Severi, S., Shi, X.P., Brus, S., Zhao, C., de Marneffe, J.F., Locorotondo, S., Shamiryan, D., Van Dal, M., Veloso, A., Lauwers, A., Niwa, M., Maex, K., Meyer, K.D., Absil, P., Jurczak, M., Biesemans, S.

“…We report for the first time on the use of a Ni fully germano-silicide (FUGESI) as a metal gate in pFETs. Using HfSiON dielectrics and comparing to Ni FUSI…”
Get full text

Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices by Severi, S., Anil, K.G., Henson, K., Lauwers, A., Veloso, A., de Marneffe, J.F., Ramos, J., Eyben, P., Vandervost, W., Jurczak, M., Biesemans, S., De Meyer, K., Pawlak, J.B., Duffy, R., Lindsay, R., Camillo-Castillo, R.A., Dachs, C.

“…This paper reports on the successful integration of truly diffusion-less (less-than-650/spl deg/C) junction formation by SPER in pMOSFETs in combination with…”
Get full text

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography by Nackaerts, A., Ercken, M., Demuynck, S., Lauwers, A., Baerts, C., Bender, H., Boulaert, W., Collaert, N., Degroote, B., Delvaux, C., de Marneffe, J.F., Dixit, A., De Meyer, K., Hendrickx, E., Heylen, N., Jaenen, P., Laidler, D., Locorotondo, S., Maenhoudt, M., Moelants, M., Pollentier, I., Ronse, K., Rooyackers, R., Van Aelst, J., Vandenberghe, G., Vandervorst, W., Vandeweyer, T., Vanhaelemeersch, S., Van Hove, M., Van Olmen, J., Verhaegen, S., Versluijs, J., Vrancken, C., Wiaux, V., Jurczak, M., Biesemans, S.

“…This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static…”
Get full text