Search Results - "Zulkifli, T.Z.A."
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1
Evaluation of five compensation circuits for electric vehicle inductively coupled power transfer (ICPT)
Published in IET Conference Proceedings (05-09-2018)“…This paper analyzed and evaluated the output power and efficiency characteristics from five new compensation circuits for inductively coupled power transfer…”
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2
5-GHz low-phase noise quadrature VCO in 0.13−μm RF CMOS process technology
Published in 2009 IEEE 10th Annual Wireless and Microwave Technology Conference (01-04-2009)“…In this paper, a 5 GHz low-phase noise RF CMOS quadrature voltage controlled oscillator (QVCO) is presented. The quadrature signals are generated by coupling…”
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3
0.18 µm fully integrated 900 MHz CMOS LNA with input and output on-chip matching for multi-standard mobile receiver
Published in 2008 International Conference on Microelectronics (01-12-2008)“…This paper presents a fully integrated single-ended low noise amplifier (LNA) for GSM (GSM850 and GSM900) and UMTS (UMTS Band V and VI). The design and…”
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4
A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application
Published in APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (01-11-2008)“…In this paper, a fully balanced 10-Gb/s differential output transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology for SDH/SONET application…”
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5
A Low-Phase Noise and High Output Swing RF LC-VCO in CMOS Technology
Published in 2006 International RF and Microwave Conference (01-09-2006)“…This paper presents the design of a 1.8-V, 3.5GHz CMOS complementary cross-coupled LC-VCO designed for WLAN IEEE 802.11a, two step frequency up-conversion…”
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6
Design, Simulation and Measurement Analysis on the S-parameters of an Inductively-degenerated Common-source Open-drain Cascode Low Noise Amplifier
Published in 2007 IEEE International Workshop on Radio-Frequency Integration Technology (01-12-2007)“…An inductively-degenerated common-source (CS) open-drain cascode LNA was designed for W-CDMA application. The operating frequency for the design was at 2.14…”
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7
Study and analysis of a 0.18 μm single-ended inductively-degenerated common-source cascode LNA under post-layout corner conditions
Published in 2007 International Conference on Intelligent and Advanced Systems (01-11-2007)“…This paper is on the study and analysis of the effects of corner conditions and post-layout simulations performed on a single-ended inductively degenerated…”
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8
Design of Voltage controlled oscillator (VCO) for ultra wideband (UWB) CMOS frequency synthesizer
Published in 2007 International Conference on Intelligent and Advanced Systems (01-11-2007)“…Voltage controlled oscillator is one of the fundamental building blocks in the frequency synthesizer architecture. A 4.224-GHz CMOS complementary cross-coupled…”
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9
Design of 2.5V, 900MHz phase-locked loop (PLL) using 0.25/spl mu/m TSMC CMOS technology
Published in 2004 IEEE International Conference on Semiconductor Electronics (2004)“…In this paper, a 2.5V, operating at 900MHz phase-locked loop implemented in 0.25/spl mu/m TSMC CMOS process technology is presented. A high speed PFD is…”
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10
Encoding characteristics of a 2 channel optical motion detector
Published in 2004 IEEE International Conference on Semiconductor Electronics (2004)“…This paper presents the design of front-end modules of a converter of an optical encoder and its key characteristics to detect motion in linear or rotary…”
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11
Design of tunable CMOS up-conversion mixer for RF integrated circuit
Published in 2004 IEEE Region 10 Conference TENCON 2004 (2004)“…A high frequency 1-3 GHz tunable pure NMOS up-conversion mixer topology is presented. The mixer is implemented in a 0.25 /spl mu/m CMOS process technology…”
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12
A monolithic 622 Mb/S half rate clock and data recovery circuit utilizing a novel linear phase detector
Published in 2004 IEEE Region 10 Conference TENCON 2004 (2004)“…Clock and data recovery (CDR) circuits are crucial components in high speed transceivers. In order to ensure synchronization between data and clock in the most…”
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13
Design and Simulation of RF-CMOS Spiral Inductors for ISM Band RFID Reader Circuits
Published in 2009 IEEE Workshop on Microelectronics and Electron Devices (01-04-2009)“…The recent popularity of RFID tags has generated research for accompanying miniature, low-power reader circuits. This work illustrates the design of RF…”
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14
Design characterization of a 1.2V 900MHz CMOS current mode down-conversion mixer with filter
Published in 2004 IEEE International Conference on Semiconductor Electronics (2004)“…The design of a CMOS down-conversion mixer using current mode multiplication technique is characterized. For a mixer, the intermediate frequency f/sub IF/ at…”
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15
A 1.8-V fully differential 2-stage OPAMP switched-capacitor delta-sigma modulator for Bluetooth application
Published in 2004 IEEE International Conference on Semiconductor Electronics (2004)“…This paper presents a fully-differential OPAMP for the switched-capacitor multi-bit delta-sigma modulator. The OPAMP has been designed using Silterra 0.18-/spl…”
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