Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget - a Bandgap Case Study

Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an...

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Bibliographic Details
Published in:	2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) pp. 21 - 24
Main Authors:	Bloem, Roderick, Larrauri, Alberto, Lengfeldner, Roland, Mateis, Cristinel, Nickovic, Dejan, Ziegler, Bjorn
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-10-2022
Subjects:	analog design Artificial neural networks Bayes methods Computational modeling Integrated circuit modeling machine learning Photonic band gap surrogate model testing Transistors Voltage
Online Access:	Get full text
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Summary:	Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an analog IC can be very limited. We leverage the recent advancements in machine learning (ML) and propose two techniques, artificial neural networks (ANN) and Gaussian processes, to learn a surrogate model from an existing test suite. We then explore the surrogate model with Bayesian optimization to guide the generation of additional tests. We use an industrial bandgap case study to evaluate the two approaches and demonstrate the virtue of Bayesian optimization in efficiently generating complementary tests with constrained effort.
ISSN:	2832-6474
DOI:	10.1109/CODES-ISSS55005.2022.00016