Search Results - "Zeitzoff, Peter M."

Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap by Ji-Woon Yang, Zeitzoff, P.M., Hsing-Huang Tseng

“…The speed performance of a double-gate (DG) FinFET CMOS with gate-source/drain (G-S/D) underlap is investigated using 2-D device and mixed-mode circuit…”
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The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs by Cheng, B., Cao, M., Rao, R., Inani, A., Vande Voorde, P., Greene, W.M., Stork, J.M.C., Zhiping Yu, Zeitzoff, P.M., Woo, J.C.S.

“…The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a…”
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Weighing in on logic scaling trends by Zietzoff, P.M., Chung, J.E.

“…In this paper, scaling trends and the associated challenges are discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors…”
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Source/Drain Parasitic Resistance Role and Electrical Coupling Effect in sub 50nm MOSFET Design by Yuan, J., Zeitoff, P.M., Woo, J.C.S.

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An improved electron and hole mobility model for general purpose device simulation by Darwish, M.N., Lentz, J.L., Pinto, M.R., Zeitzoff, P.M., Krutsick, T.J., Hong Ha Vuong

“…A new, comprehensive, physically-based, semiempirical, local model for transverse-field dependent electron and hole mobility in MOS transistors is presented…”
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Correcting effective mobility measurements for the presence of significant gate leakage current by Zeitzoff, P.M., Young, C.D., Brown, G.A., Yudong Kim

“…A physically based correction for the impact of gate leakage current on the extraction of the effective mobility in MOSFETs has been derived that allows…”
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A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions by Zeitzoff, P.M., Chung, J.E.

“…The IC industry has been rapidly and consistently scaling the design rules, increasing the chip and wafer size, and cleverly improving the design of devices…”
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CMOSFET scaling through the end of the roadmap by Zeitzoff, P.M.

“…The scaling of CMOS transistors is discussed from the perspective of the 2005 International Technology Roadmap for Semiconductors. Numerous critical scaling…”
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MOSFET scaling trends and challenges through the end of the roadmap by Zeitzoff, P.M.

“…The overall trends and issues in logic MOSFET scaling are discussed from the perspective of the 2003 International Technology Roadmap for Semiconductors…”
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A simplified approach for quasi-three-dimensional modeling of npn transistors by Zeitzoff, P.M.

“…The transistors are modeled by connecting, in parallel, appropriate combinations of five Gummel-Poon-type compact circuit models. The models are extracted…”
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An isolated vertical n-p-n transistor in an n-well CMOS process by Zeitzoff, P.M., Anagnostopoulos, C.N., Wong, K.Y., Brandt, B.P.

“…Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source…”
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Technology CAD at AT&T by Lloyd, Peter, McAndrew, Colin C., McLennan, Michael J., Nassif, Sani R., Singhal, Kishore, Singhal, Kumud, Zeitzoff, Peter M., Darwish, Mohamed N., Haruta, Ken, Lentz, Janet L., Vuong, Hong-Ha, Pinto, Mark R., Rafferty, Conor S., Kizilyalli, Isik C.

“…Technology computer-aided design (TCAD) is essential to the design of modern integrated circuit fabrication processes. TCAD tools must not only model real…”
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