Search Results - "Yongrong Zuo"

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration by Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Godbole, Kunal, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Cho, Thomas Byunghak

“…A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz,…”
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A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS by Seth, Siddharth, Dae Hyun Kwon, Venugopalan, Sriramkumar, Sang Won Son, Yongrong Zuo, Bhagavatula, Venumadhav, Jaehyun Lim, Dongjin Oh, Cho, Thomas Byunghak

“…We present a highly configurable, low-power, low-area, low-EVM, SAW-less transmitter (TX) architecture that is based on a dynamically biased power mixer. All…”
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A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM by Wanghua Wu, Chih-Wei Yao, Godbole, Kunal, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Verma, Ashutosh, Lu, Ivan Siu-Chuang, Sang Won Son, Cho, Thomas Byunghak

“…We present a low jitter, DTC-based analog fractional-N PLL with novel, background DTC gain calibration and reference clock duty cycle correction for high…”
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A dynamically-biased 2G/3G/4G multi-band transmitter with > 4dBm Pout, < −65dBc CIM3 and < −157dBc/Hz out-of-band noise in 28nm CMOS by Seth, Siddharth, Kwon, Daehyun, Venugopalan, Sriramkumar, Sang Won Son, Yongrong Zuo, Bhagavatula, Venumadhav, Lim, Jaehyun, Dongjin Oh, Cho, Thomas

“…We present a highly-configurable, low-power, low-area, SAW-less TX architecture that is based on a dynamically-biased power mixer. All FDD/TDD bands for 4G LTE…”
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A 28-nm 75-fs rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction by Wu, Wanghua, Yao, Chih-Wei, Godbole, Kunal, Ni, Ronghua, Chiang, Pei-Yuan, Han, Yongping, Zuo, Yongrong, Verma, Ashutosh, Lu, Ivan Siu-Chuang, Son, Sang Won, Cho, Thomas Byunghak

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A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS by Lee, Jongwoo, Son, Ki Yong, Lim, Hyungsun, Jeong, Daechul, Jong, Ilyong, Baek, Sanghyun, Lee, Jae Hoon, Ni, Ronghua, Zuo, Yongrong, Yao, Chih-Wei, Heo, Seungchan, Han, Sangwook, Cho, Thomas Byunghak, Kang, Inyup, Lee, Joonhee, Kang, Byoungjoong, Bae, Jeongyeol, Jang, Jaehyuk, Oh, Seunghyun, Chang, Ji-Soo, Kang, Sanghoon

“…The world's first single-chip RF transceiver to support 5G sub-6-GHz new radio (NR) and longterm evolution (LTE) E-UTRA New Radio-Dual Connectivity (EN-DC) in…”
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A 28-nm 75-fsrms Analog Fractional- N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction by Wu, Wanghua, Yao, Chih-Wei, Godbole, Kunal, Ni, Ronghua, Chiang, Pei-Yuan, Han, Yongping, Zuo, Yongrong, Verma, Ashutosh, Lu, Ivan Siu-Chuang, Son, Sang Won, Cho, Thomas Byunghak

“…An analog fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> sampling phase-locked loop (PLL) is presented. It achieves…”
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A 28-nm 75-fsrms Analog Fractional-[Formula Omitted] Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction by Wu, Wanghua, Chih-Wei, Yao, Godbole, Kunal, Ni, Ronghua, Pei-Yuan, Chiang, Han, Yongping, Zuo, Yongrong, Verma, Ashutosh, Ivan Siu-Chuang Lu, Son, Sang Won, Cho, Thomas Byunghak

“…An analog fractional-[Formula Omitted] sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a…”
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A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration by Yao, Chih-Wei, Ni, Ronghua, Lau, Chung, Wu, Wanghua, Godbole, Kunal, Zuo, Yongrong, Ko, Sangsoo, Kim, Nam-Seog, Han, Sangwook, Jo, Ikkyun, Lee, Joonhee, Han, Juyoung, Kwon, Daehyeon, Kim, Chulho, Kim, Shinwoong, Son, Sang Won, Cho, Thomas Byunghak

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21.6 A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS by Lee, Jongwoo, Han, Sangwook, Lee, Joonhee, Kang, Byoungjoong, Bae, Jeongyeol, Jang, Jaehyuk, Oh, Seunghyun, Ahn, Suseob, Kang, Sanghoon, Bui, Quang-Diep, Son, Kiyong, Lim, Hyungsun, Jeong, Daechul, Ni, Ronghua, Zuo, Yongrong, Jong, Ilyong, Yao, Chih-Wei, Heo, Seungchan, Cho, Thomas Byunghak, Kang, Inyup

“…To carry on the explosion of mobile data traffic, cellular networks have evolved to enhance air capacity with emerging 5G New Radio (NR) technologies. Thanks…”
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24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and −78dBc fractional spur for cellular RFICs by Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Godbole, Kunal, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Cho, Thomas Byunghak

“…To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires…”
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Extremely low-power, multi-Gigabit electrical signaling for parallel optical modules by Kiamilev, F., Kramer, J., Ekman, J., Xingle Wang, Yongrong Zuo

“…This paper describes a physical interface for short distance electrical links that are typically used to link parallel optical modules into the system. This…”
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Power -efficient dual -rate gigabit transceiver design by Zuo, Yongrong

“…This work describes a dual-rate optical transceiver designed for power-efficient connections within and between modern high-speed digital systems. The…”
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Current-bleeding-fast power-on for VCSEL-based giga-bit optical transceivers by Xingle Wang, Kiamilev, F., Ping Gui, Ziaoqing Wang, Ekman, J., Yongrong Zuo

“…We present a power-efficient solution for reducing VCSEL-based optical transmitter power-on delay. At 1.5 Gps our 0.5 /spl mu/m CMOS demo system recorded a…”
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Power-efficient dual-rate gigabit transceiver design by Zuo, Yongrong

“…This work describes a dual-rate optical transceiver designed for power-efficient connections within and between modern high-speed digital systems. The…”
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