Search Results - "Yin, K.M."

Mathematical Model of Proton Exchange Membrane Fuel Cell with Consideration of Water Management by Yin, K.-M., Hsuen, H.-K.

“…One‐dimensional model on the membrane electrode assembly (MEA) of proton exchange membrane fuel cell is proposed, where the membrane hydration/dehydration and…”
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Demonstration of Low Vt Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a Dy2O3 Cap Layer by Yu, H.Y, Chang, S.Z, Veloso, A, Lauwers, A, Adelmann, C, Onsia, B, Lehnen, P, Kauerauf, T, Brus, S, Yin, K.M, Absil, P, Biesemans, S

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Demonstration of Low V Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a \hbox\hbox Cap Layer by Yu, H.Y., Chang, S.Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Lehnen, P., Kauerauf, T., Brus, S., Yin, K.M., Absil, P., Biesemans, S.

“…This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide…”
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Demonstration of low Vt Ni-FUSI N-MOSFETs with SiON dielectrics by using a Dy2O3 cap layer by YU, H. Y, CHANG, S. Z, ABSIL, P, BIESEMANS, S, VELOSO, A, LAUWERS, A, ADELMANN, C, ONSIA, B, LEHNEN, P, KAUERAUF, T, BRUS, S, YIN, K. M

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Demonstration of Metal-Gated Low V n-MOSFETs Using a Poly- \hbox\hbox/\hbox Gate Stack With a Scaled EOT Value by H.Y. Yu, Singanamalla, R., Ragnarsson, L.-A., V.S. Chang, H.-J. Cho, Mitsuhashi, R., Adelmann, C., Van Elshocht, S., Lehnen, P., S.Z. Chang, K.M. Yin, Schram, T., Kubicek, S., De Gendt, S., Absil, P., De Meyer, K., Biesemans, S.

“…In this letter, we report that by using a thin dysprosium oxide (Dy 2 O 3 )cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (V t…”
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Demonstration of metal-gated low Vt n-MOSFETs using a poly -Si /TaN/Dy2O3/SiON gate stack with a scaled EOT value by YU, H. Y, SINGANAMALLA, R, YIN, K. M, SCHRAM, T, KUBICEK, S, DE GENDT, S, ABSIL, P, DE MEYER, K, BIESEMANS, S, RAGNARSSON, L.-A, CHANG, V. S, CHO, H.-J, MITSUHASHI, R, ADELMANN, C, VAN ELSHOCHT, S, LEHNEN, P, CHANG, S. Z

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Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack by Veloso, A., Yu, H.Y., Lauwers, A., Chang, S.Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O′Sullivan, B.J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K.M., Niwa, M., Hoffmann, T., Absil, P., Jurczak, M., Biesemans, S.

“…This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF)…”
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The investigation of crack mechanism for Tyranno-SA SiC/SiC composites with ESI method by Yan, J.Y, Chen, C.W, Fang, P.C, Yin, K.M, Chen, F.R, Katoh, Y, Kohyama, A, Kai, J.J

“…In order to clarify the fracture mechanism of frictional stress and bonding strength in SiC/SiC composites, the mechanical test and HRTEM equipped with…”
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Study of helium bubble formation in SiCf/PyC/β-SiC composites by dual-beam irradiation by Duh, T.S, Yin, K.M, Yan, J.Y, Fang, P.C, Chen, C.W, Kai, J.J, Chen, F.R, Katoh, Y, Kohyama, A

“…The formation of helium bubbles in the advanced SiC composites, Tyranno-SA SiC/PyC/β-SiC (TSA) and Hi-Nicalon Type-S SiC/PyC/β-SiC (HNS), implanted with helium…”
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Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases by Yu, H.Y., Chang, S.Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Van Elshocht, S., Singanamalla, R., Demand, M., Vos, R., Kauerauf, T., Brus, S., Shi, X., Kubicek, S., Vrancken, C., Mitsuhashi, R., Lehnen, P., Kittl, J., Niwa, M., Yin, K.M., Hoffmann, T., Degendt, S., Jurczak, M., Absil, P., Biesemans, S.

“…This paper reports a novel approach to implement low V t Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host…”
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Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application by Hsu, P.F., Hou, Y.T., Yen, F.Y., Chang, V.S., Lim, P.S., Hung, C.L., Yao, L.G., Jiang, J.C., Lin, H.J, Chiou, J.M., Yin, K.M., Lee, J.J, Hwang, R.L., Jin, Y., Chang, S.M., Tao, H.J., Chen, S.C., Liang, M.S., Ma, T.P

“…This paper reports the fabrication of MOSFETs with dual metal gate electrodes. Low threshold voltage (Vt) was achieved using TaC for nFETs and MoNx for pFETs…”
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Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack by Veloso, A., Yu, H.Y., Lauwers, A., Chang, S.Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O'Sullivan, B.J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K.M., Niwa, M., Hoffmann, T., Absil, P., Jurczak, M., Biesemans, S.

“…This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF)…”
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