Search Results - "Yang, Wouns"
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A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies
Published in 2013 IEEE International Electron Devices Meeting (01-12-2013)“…This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC…”
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Electrical Failure Analysis Methodology for DRAM of 80nm era and beyond using Nanoprober Technique
Published in 2007 IEEE International Conference on Microelectronic Test Structures (01-03-2007)“…In this paper, the electrical failure analysis for DRAM of design rule as 80 nm and beyond by using nanoprober technique was described. We have successfully…”
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Conference Proceeding
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Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain
Published in 2006 European Solid-State Device Research Conference (01-09-2006)“…Gate induced drain leakage (GIDL) characteristics were investigated with the recessed channel array transistor (RCAT) for DRAM, using the elevated source drain…”
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Shallow Trench Isolation Characteristics with High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide for Deep-Submicron CMOS Technologies
Published in Japanese Journal of Applied Physics (01-03-1998)“…Shallow trench isolation (STI) characteristics were systematically studied based on various deposition conditions of high-density-plasma (HDP) chemical vapor…”
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Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond
Published in 2006 International Electron Devices Meeting (01-12-2006)“…For the first time, we have successfully fabricated fully integrated advanced bulk FinFETs featuring partially insulating oxide layers under source/drain…”
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Conference Proceeding -
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A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell
Published in 2007 IEEE International Electron Devices Meeting (01-12-2007)“…We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si…”
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Conference Proceeding -
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A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon
Published in IEEE transactions on electron devices (01-10-2004)“…Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully…”
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A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon
Published in IEEE transactions on electron devices (01-10-2004)“…Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully…”
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A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n super(+)-doped polysilicon
Published in IEEE transactions on electron devices (01-01-2004)“…Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully…”
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Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories
Published in Japanese Journal of Applied Physics (01-04-2008)Get full text
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Investigation of Body Bias Dependence of Gate-Induced Drain Leakage Current for Body-Tied Fin Field Effect Transistor
Published in Japanese Journal of Applied Physics (01-09-2008)Get full text
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Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer
Published in 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual (01-04-2007)“…This paper presents a detailed analysis of the reliability characteristics of partially-insulated FinFETs (PI-FinFETs) where a new source/drain structure was…”
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Conference Proceeding -
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A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique
Published in 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers (2006)“…A full FinFET DRAM core which consists of McFETs for both the sense amplifiers and the sub-word drivers, as well as FinFETs for the memory cell array has been…”
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Conference Proceeding -
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New anti-punchthrough design for buried channel PMOSFET
Published in 27th European Solid-State Device Research Conference (1997)Get full text
Conference Proceeding -
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A new process integration-P/sup 3/ (pre poly plug)-for giga bit DRAM era
Published in 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) (1999)“…By utilizing not only the suitable topology generated by underlying layers but also advanced processes such as poly-oxide CMP, highly selective etch, PR…”
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Comparative study of several anti-punchthrough designs for buried channel PMOSFET
Published in 1997 55th Annual Device Research Conference Digest (1997)“…As CMOS technology is scaled down, buried channel (BC) PMOS has been replaced by surface channel (SC) PMOS due to the poor short channel effect (SCE) in BC…”
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Conference Proceeding