Search Results - "Yang, Jeong Suk"

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  1. 1

    Suppressing Undesired Channel Length‐Dependent Electrical Characteristics of Fully Integrated InGaZnO Thin‐Film Transistors via Defect Control Layer by Kim, Kyung Min, Yang, Jeong Suk, Kim, Hyung Tae, Han, Inhyo, Jung, Sang‐Hoon, Yang, Joon‐Young, Ha, Yong Min, Yoon, Soo Young, Kim, Hyun Jae

    Published in Advanced electronic materials (01-01-2023)
    “…Demand for increased scalability of oxide thin‐film transistors (TFTs) continues to rise, along with the need for ever‐higher integration densities and driving…”
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    Journal Article
  2. 2

    Hole Transport Enhancing Effects of Polar Solvents on Poly(3,4-ethylenedioxythiophene):Poly(styrene sulfonic acid) for Organic Solar Cells by Yang, Jeong Suk, Oh, Sang Hoon, Kim, Dong Lim, Kim, Si Joon, Kim, Hyun Jae

    Published in ACS applied materials & interfaces (24-10-2012)
    “…This study analyzed the properties of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonic acid) (PEDOT:PSS) thin-films prepared by spin-coating solutions…”
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    Journal Article
  3. 3

    A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM by Cho, Uk-Rae, Kim, Tae-Hyoung, Yoon, Yong-Jin, Lee, Jong-Cheol, Bae, Dae-Gi, Kim, Nam-Seog, Kim, Kang-Young, Son, Young-Jae, Yang, Jeong-Suk, Sohn, Kwon-Il, Kim, Sung-Tae, Lee, In-Yeol, Lee, Kwang-Jin, Kang, Tae-Gyoung, Kim, Su-Chul, Ahn, Kee-Sik, Byun, Hyun-Geun

    Published in IEEE journal of solid-state circuits (01-11-2003)
    “…A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the…”
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    Journal Article
  4. 4

    Effects of ZnO Nanoparticles on P3HT:PCBM Organic Solar Cells with DMF-Modulated PEDOT:PSS Buffer Layers by Oh, Sang Hoon, Heo, Seung Jin, Yang, Jeong Suk, Kim, Hyun Jae

    Published in ACS applied materials & interfaces (27-11-2013)
    “…In this study, we investigated hybrid bulk heterojunction organic solar cells containing ZnO nanoparticles blended with poly(3-hexylthiophene) (P3HT) and…”
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    Journal Article
  5. 5

    A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM by Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun

    “…A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines…”
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    Conference Proceeding