Search Results - "Woon, W.Y."

Rapid thermal process driven intra-die device variations by Tsai, C.H., Aboy, M., Pelaz, L., Hsu, Y.H., Woon, W.Y., Timans, P.J., Lee, C.K.

“…Intra-die device variation due to pattern layout effects associated with the development of ultra-fast annealing processes is one of the major scaling…”
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Achieving junction stability in heavily doped epitaxial Si:P by Tsai, C.H., Hsu, Y.H., Santos, I., Pelaz, L., Kowalski, J.E., Liou, J.W., Woon, W.Y., Lee, C.K.

“…Junction stability and donor deactivation in silicon at high doping limit has been a long-standing issue in advanced semiconductor devices. Recently, heavily…”
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Robustness of large-area suspended graphene under interaction with intense laser by Kuramitsu, Y., Minami, T., Hihara, T., Sakai, K., Nishimoto, T., Isayama, S., Liao, Y. T., Wu, K. T., Woon, W. Y., Chen, S. H., Liu, Y. L., He, S. M., Su, C. Y., Ota, M., Egashira, S., Morace, A., Sakawa, Y., Abe, Y., Habara, H., Kodama, R., Döhl, L. N. K., Woolsey, N., Koenig, M., Kumar, H. S., Ohnishi, N., Kanasaki, M., Asai, T., Yamauchi, T., Oda, K., Kondo, Ko, Kiriyama, H., Fukuda, Y.

“…Graphene is known as an atomically thin, transparent, highly electrically and thermally conductive, light-weight, and the strongest 2D material. We investigate…”
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Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling by Liao, S., Yang, L., Chiu, T.K., You, W.X., Wu, T.Y., Yang, K.F., Woon, W.Y., Ho, W.D., Lin, Z.C., Hung, H.Y., Huang, J.C., Huang, S.T., Tsai, M.C., Yu, C.L., Chen, S.H., Hu, K.K., Shih, C.C., Chen, Y.T., Liu, C.Y., Lin, H.Y., Chung, C.T., Su, L., Chou, C.Y., Shen, Y.T., Chang, C.M., Lin, Y.T., Lin, M.Y., Lin, W.C., Chen, B.H., Hou, C.S., Lai, F., Chen, X., Wu, J., Lin, C.K., Cheng, Y.K., Lin, H.T., Ku, Y.C., Lin, S.S., Lu, L.C., Jang, S.M., Cao, M.

“…This study establishes the groundwork for an industry-applicable, integrated nanosheet-based monolithic CFET process architecture with a gate pitch of 48nm. By…”
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