Search Results - "Winderickx, G."

Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates by De Jaeger, B., Bonzom, R., Leys, F., Richard, O., Steenbergen, J. Van, Winderickx, G., Moorhem, E. Van, Raskin, G., Letertre, F., Billon, T., Meuris, M., Heyns, M.

“…A key challenge in the engineering of Ge MOSFETs is to develop a proper Ge surface passivation technique prior to high-k dielectric deposition to obtain low…”
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Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors by Van Huylenbroeck, S., Decoutere, S., Venegas, R., Jenei, S., Winderickx, G.

“…Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low…”
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Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability by Mitard, J., De Jaeger, B., Leys, F.E., Hellings, G., Martens, K., Eneman, G., Brunco, D.P., Loo, R., Lin, J.C., Shamiryan, D., Vandeweyer, T., Winderickx, G., Vrancken, E., Yu, C.H., De Meyer, K., Caymax, M., Pantisano, L., Meuris, M., Heyns, M.M.

“…We report on a 65 nm Ge pFET with a record performance of I on = 478muA/mum and I off,s = 37nA/mum @V dd = -1V. These improvements are quantified and…”
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High performance Ge pMOS devices using a Si-compatible process flow by Zimmerman, P., Nicholas, G., De Jaeger, B., Kaczer, B., Stesmans, A., Ragnarsson, L.-A., Brunco, D.P., Leys, F.E., Caymax, M., Winderickx, G., Opsomer, K., Meuris, M., Heyns, M.M.

“…Ge pMOS mobilities up to 358 cm 2 /Vs are demonstrated using a Si-compatible process flow without the incorporation of strain. EOT is approximately 12 Aring…”
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Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STI by Mitard, J., Shea, C., DeJaeger, B., Pristera, A., Wang, G., Houssa, M., Eneman, G., Hellings, G., Wang, W.E., Lin, J.C., Leys, F.E., Loo, R., Winderickx, G., Vrancken, E., Stesmans, A., DeMeyer, K., Caymax, M., Pantisano, L., Meuris, M., Heyns, M.

“…For the first time, an STI module is integrated in an advanced 70 nm Ge-pFET technology allowing EOT scaling down to 0.85 nm. Gate leakage is kept below…”
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Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line by De Jaeger, B., Houssa, M., Satta, A., Kubicek, S., Verheyen, P., Van Steenbergen, J., Croon, J., Kaczer, B., Van Elshocht, S., Delabie, A., Kunnen, E., Sleeckx, E., Teerlinck, I., Lindsay, R., Schram, T., Chiarella, T., Degraeve, R., Conard, T., Poortmans, J., Winderickx, G., Boullart, W., Schaekers, M., Mertens, P.W., Caymax, M., Vandervorst, W., Van Moorhem, E., Biesemans, S., De Meyer, K., Ragnarsson, L., Lee, S., Kota, G., Raskin, G., Mijlemans, P., Autran, J.-L., Afanas'ev, V., Stesmans, A., Meuris, M., Heyns, M.

“…We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process…”
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A 400GHz fMAX fully self-aligned SiGe:C HBT architecture by Van Huylenbroeck, S., Sibaja-Hernandez, A., Venegas, R., You, S., Winderickx, G., Radisic, D., Lee, W., Ong, P., Vandeweyer, T., Nguyen, N.D., De Meyer, K., Decoutere, S.

“…An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An f MAX value of 400 GHz is…”
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The future of high- K on pure germanium and its importance for Ge CMOS by Meuris, M., Delabie, A., Van Elshocht, S., Kubicek, S., Verheyen, P., De Jaeger, B., Van Steenbergen, J., Winderickx, G., Van Moorhem, E., Puurunen, R.L., Brijs, B., Caymax, M., Conard, T., Richard, O., Vandervorst, W., Zhao, C., De Gendt, S., Schram, T., Chiarella, T., Onsia, B., Teerlinck, I., Houssa, M., Mertens, P.W., Raskin, G., Mijlemans, P., Biesemans, S., Heyns, M.M.

“…A comparison between atomic layer chemical vapor deposition (ALCVD) and metal organic chemical vapor deposition (MOCVD) HfO 2 layers on Ge indicate that ALCVD…”
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P2-034: Deletion of genes responsible for vesicular transport in yeast causes mislocalization and enhanced toxicity of α-synuclein by Zabrocki, Piotr, Pellens, Klaartje, Van Leuven, Fred, Winderickx, Joris G.

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Integration of III-V on Si for High-Mobility CMOS by Waldron, N., Gang Wang, Ngoc Duy Nguyen, Orzali, T., Merckling, C., Brammertz, G., Ong, P., Winderickx, G., Hellings, G., Eneman, G., Caymax, M., Meuris, M., Horiguchi, N., Thean, A.

“…In this paper we present results from an InGaAs/InP implant free quantum well device integrated fully in a Si CMOS processing line. The virtual InP substrates…”
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P2-033: Molecular determinants of the phosphorylation and aggregation of human protein tau in a yeast model by Winderickx, Joris G., Vanhelmont, Thomas, Vandebroek, Tom, Pellens, Klaartje, De Vos, Ann, Terwel, Dick, Zabrocki, Piotr, Van Leuven, Fred

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Selective Epitaxial Growth of GaAs on Ge Substrates with a SiO2 Pattern by Brammertz, G, Caymax, M, Mols, Y, Degroote, S, Leys, M, Van Steenbergen, J, Winderickx, G, Borghs, G, Meuris, M

“…Proceedings of the 210th Meeting of The Electrochemical Society, Cancun, Mexico, October 29-November 3, 2006 We have selectively grown thin epitaxial GaAs…”
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A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process by Donkers, J.J.T.M., Vanhoucke, T., Vleugels, F., Winderickx, G., Kunnen, E., Peeters, S., Baute, D., De Vos, B., Vandeweyer, T., Loo, R., Venegas, R., Kramer, M.C.J.C.M., Pijper, R., Voogt, F.C., Decoutere, S., Hijzen, E.A., Van Huylenbroeck, S., Choi, L.J., Meunier-Beillard, P., Sibaja-Hernandez, A., Boccardi, G., van Noort, W., Hurkx, G.A.M.

“…In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this…”
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Ge Deep Sub-Micron HiK/MG pFET with Superior Drive Compared to Si HiK/MG State-of-the-Art Reference by DeJaeger, B., Kaczer, B., Zimmerman, P., Opsomer, K., Winderickx, G., Van Steenbergen, J., Van Moorhem, E., Bonzom, R., Leys, F., Arena, C., Bauer, M., Werkhoven, C., Meuris, M., Heyns, M.

“…This paper presents results on conventional, deep sub-micron short-channel Ge p-and nFET devices with a HiK/MG gate stack and NiGe source/drain regions. It is…”
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High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene by Jenei, S., Decoutere, S., Winderickx, G., Struyf, H., Tokei, Z., Vervoort, I., Vos, I., Jaenen, P., Carbonell, L., De Jaeger, B., Donaton, R.A., Vanhaelemeersch, S., Maex, K., Nauwelaers, B.

“…Thick Cu single damascene inductors with very high Q factors are integrated on top of a standard aluminum 3LM BEOL process. Obtained Q factors are more than…”
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Detector diodes and test devices fabricated in high resistivity SOI wafers by Bosisio, L., Focardi, E., Forti, F., Kashigin, S., Dierickx, B., Wouters, D., Willems, G., Winderickx, G., Debusschere, I., Simoen, E., Claeys, C., Maes, H., Hermans, L., Heijne, E.H.M., Jarron, P., Campbell, M., Anghinolfi, F., Aspell, P., Delpierre, P., Sauvage, D., Habrard, M.C.

“…A novel approach to monolithic pixel detectors based on SOI (silicon-on-insulator) wafers with high-resistivity substrates is being pursued by the CERN RD-19…”
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