Implementation of a deep space receiver on 350K gate GaAs gate arrays

Implementation of a deep space receiver on 350K gate GaAs gate arrays

A set of three GaAs ASICs have been designed which together form part of the Block V Digital Receiver. Each ASIC contains approximately 150K-170K used gates. This paper describes the design methodology for the GaAs ASICs, which ensures successful timing, testability, and functionality.

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Bibliographic Details
Published in:IEEE GaAs IC Symposium, 1993
Main Authors: Burke, Gary R, Chow, Terrence W, Graham, J Scott, Kowalski, James E, Whitaker, William D, Johnson, Robert A
Format: Journal Article
Language:English
Published: 01-01-1993
Online Access:Get full text
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Description
Summary:A set of three GaAs ASICs have been designed which together form part of the Block V Digital Receiver. Each ASIC contains approximately 150K-170K used gates. This paper describes the design methodology for the GaAs ASICs, which ensures successful timing, testability, and functionality.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISBN:0780313933
9780780313934
DOI:10.1109/GAAS.1993.394481