Search Results - "Wedler, M."
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Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2008)“…We propose a methodology to formally prove protocol compliance for communication blocks in System-on-Chip (SoC) designs. In this methodology, a set of…”
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A Normalization Method for Arithmetic Data-Path Verification
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2007)“…We propose a normalization technique for verifying arithmetic circuits in a bounded model-checking environment. Our technique operates on the arithmetic…”
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Structural FSM traversal
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-05-2004)“…This paper discusses a "structural" technique for traversing the state space of a finite state machine (FSM) and its application to equivalence checking of…”
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P01-10 Cell painting PLUS: an enhanced multiplexed phenotypic assay for chemical hazard screening
Published in Toxicology letters (01-09-2024)Get full text
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Normalization at the arithmetic bit level
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005 (13-06-2005)“…We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit…”
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Conference Proceeding
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Arithmetic reasoning in DPLL-based SAT solving
Published in Proceedings Design, Automation and Test in Europe Conference and Exhibition (2004)“…We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an…”
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Formal hardware/software co-verification by interval property checking with abstraction
Published in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) (05-06-2011)“…Ensuring functional correctness of hardware and software is a bottleneck in every design process of Embedded Systems. This paper proposes an approach to…”
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Conference Proceeding -
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Exploiting state encoding for invariant generation in induction-based property checking
Published in ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) (2004)“…We focus on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to create a…”
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Conference Proceeding -
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Improving structural FSM traversal by constraint-satisfying logic simulation
Published in Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 (2002)“…We increase the reasoning power of the Record & Play algorithm for structural FSM traversal (Stoffel and Kunz, 1997), by incorporating a constraint-satisfying…”
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Conference Proceeding -
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Transition-by-transition FSM traversal for reachability analysis in bounded model checking
Published in International Conference on Computer Aided Design: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design; 06-10 Nov. 2005 (31-05-2005)“…In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a…”
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Conference Proceeding -
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Transition-by-transition FSM traversal for reachability analysis in bounded model checking
Published in ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 (2005)“…In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a…”
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Conference Proceeding -
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System verification of concurrent RTL modules by compositional path predicate abstraction
Published in DAC Design Automation Conference 2012 (03-06-2012)“…A new methodology for formal system verification of System-on-Chip (SoC) designs is proposed. It does not only ensure correctness of the system-level models…”
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Conference Proceeding -
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STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra
Published in 2011 Design, Automation & Test in Europe (01-03-2011)“…This paper presents a new SMT solver, STABLE, for formulas of the quantifier-free logic over fixed-sized bit vectors (QF-BV). The heart of STABLE is a…”
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Conference Proceeding -
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HLA-DRB1 and anti-cyclic citrullinated peptide antibody production in rheumatoid arthritis
Published in International Archives of Allergy and Immunology (01-08-2005)“…Anti-cyclic citrullinated peptide antibodies (anti-CCP) are a new diagnostic marker for rheumatoid arthritis (RA), which shows a specificity of 97% and a…”
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Preparation and structural characterization of dioxane-coordinated alkali metal bis(trimethylsilyl)amides
Published in Inorganic chemistry (01-09-1992)Get full text
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Using RTL Statespace Information and State Encoding for Induction Based Property Checking
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1; 03-07 Mar. 2003 (03-03-2003)“…This paper focuses on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to…”
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Conference Proceeding