Search Results - "Wassick, Thomas"
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1
Chip Power-Frequency Scaling in 10/7nm Node
Published in IEEE access (01-01-2020)“…The 10/7nm node has been introduced by all major semiconductor manufacturers (Intel, TSMC, and Samsung Electronics). This paper looks at the power-performance…”
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Journal Article -
2
Creep characterization of solder bumps using nanoindentation
Published in Mechanics of time-dependent materials (01-08-2017)“…Current nanoindentation techniques for the measurement of creep properties are applicable to viscoplastic materials with negligible elastic deformations. A new…”
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Journal Article -
3
On the path to AI hardware via chiplet integration enabled by high density organic substrates
Published in 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC) (01-01-2023)“…In this study, the heterogeneous integration of three mixed test chips is investigated and designed for AI hardware. An high bandwidth memory (HBM) test die, a…”
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Conference Proceeding -
4
3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
Published in IEEE transactions on components, packaging, and manufacturing technology (2011) (01-05-2021)“…In this letter, we have demonstrated a packaging technique for 3-D IC with Cu back-end-of-the line (BEOL) on a mixed pitch (55 and <inline-formula> <tex-math…”
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Journal Article -
5
Finite Element Modeling of C4 Cracking in a Large Die Large Laminate Coreless Flip Chip Package
Published in 2016 IEEE 66th Electronic Components and Technology Conference (ECTC) (01-05-2016)“…BGA substrates made of organic materials are now industry standard as they provide significant advantages over the ceramic dielectric-based predecessors in…”
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Conference Proceeding -
6
Reliable Chiplet Integration on High Density Laminate (2.XD) for AI Hardware
Published in 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) (28-05-2024)“…In this study, High Density Laminate with a bonded organic interposer (2.XD Laminate) is described and evaluated. The 2.XD laminate has <3 μm/3 μm L/S in the…”
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Conference Proceeding -
7
Scalable Advanced DBHi Chiplet Package Using Silicon Bridge With 30 µm-Pitch Solder Joints
Published in 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) (28-05-2024)“…Direct-bonded heterogeneous integration (DBHi) is a unique chiplet packaging technology using directly-bonded silicon bridges as high-density inter-chip…”
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Conference Proceeding -
8
Direct Bonded Heterogeneous Integration (DBHi): Surface Bridge Approach for Die Tiling
Published in 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC) (01-05-2023)“…With a continuous focus to maximize computational performance by optimizing package size and reducing fabrication costs, this paper presents the most recent…”
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Conference Proceeding -
9
Direct Bonded Heterogeneous Integration (DBHi) Si Bridge
Published in 2021 IEEE 71st Electronic Components and Technology Conference (ECTC) (01-06-2021)“…We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between…”
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Conference Proceeding -
10
3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55\ \mu\mathrm-75\ \mu \mathrm Mixed Pitch Interconnections on High Density Laminate
Published in 2021 IEEE 71st Electronic Components and Technology Conference (ECTC) (01-06-2021)“…In this work, a 3D Die-Stack on Substrate (3D-DSS) bonding process has been developed to demonstrate a 3D die stack that has been joined to a mixed pitch ( 5\…”
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Conference Proceeding -
11
Comparison of electromigration behaviors of SnAg and SnCu solders
Published in 2009 IEEE International Reliability Physics Symposium (01-04-2009)“…Two commonly used Pb-free solders, SnAg and SnCu, are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based…”
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Conference Proceeding -
12
Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules
Published in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) (01-05-2022)“…3D die stacking of logic and memory die can greatly enhance system performance, by enabling the logic die to have high bandwidth, low latency, low energy…”
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Conference Proceeding -
13
Stress reduction methods within the Far Back End of Line (FBEOL) for fine pitch and 2.5D/3D packaging configurations
Published in 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) (01-05-2016)“…Fine pitch interconnects combined with 2.5D/3D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to…”
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Conference Proceeding -
14
Inspection / Metrology Evaluation of Fine Pitch Test Vehicles for Advanced Packages
Published in 2019 International Conference on Electronics Packaging (ICEP) (01-04-2019)“…The demand for integrated silicon packages is driving packaging advancements for increasingly fine circuit pattern designs. Due to the thinner copper and finer…”
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Conference Proceeding -
15
Chip-Package Interaction Challenges for Large Die Applications
Published in 2018 IEEE 68th Electronic Components and Technology Conference (ECTC) (01-05-2018)“…To enable higher computing power in a single chip, there is demand for increasing die size for high performance applications in advanced nodes. Due to the weak…”
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Conference Proceeding -
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Inspection/metrology benchmarking on fine pitch design substrate for advanced packages
Published in 2017 International Conference on Electronics Packaging (ICEP) (01-04-2017)“…Integrated silicon packages, such as System in Package, are becoming more popular as electronic packaging solutions, and this technology is driving the need…”
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Conference Proceeding -
17
Electromigration and thermal migration in Pb-free interconnects
Published in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC) (01-05-2015)“…A set of experiments designed to understand the evolution of electromigration damage in Pb-free interconnects was conducted. It is found that the degree of EM…”
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Conference Proceeding -
18
Effect of Ag and Cu content in Sn based Pb-free solder on electromigration
Published in 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) (01-05-2014)“…The effect of Ag and Cu concentrations on the electromigration of Pb-free solder was investigated. A nine cell experiment with Ag concentrations ranging from…”
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Conference Proceeding -
19
Electrochemical reactions in solder mask of flip chip-plastic ball grid array package
Published in 2013 IEEE 63rd Electronic Components and Technology Conference (01-05-2013)“…A typical flip chip plastic ball grid array (FC-PBGA) module utilizes a laminate substrate, which has a solder mask layer at the surface and a number of…”
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Conference Proceeding -
20
Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology
Published in 2012 IEEE 62nd Electronic Components and Technology Conference (01-05-2012)“…A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to…”
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Conference Proceeding