Search Results - "Wassick, Thomas"

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  1. 1

    Chip Power-Frequency Scaling in 10/7nm Node by Oldiges, Phil, Vega, Reinaldo, Utomo, Henry K., Lanzillo, Nick A., Wassick, Thomas, Li, Juntao, Wang, Junli, Shahidi, Ghavam G.

    Published in IEEE access (01-01-2020)
    “…The 10/7nm node has been introduced by all major semiconductor manufacturers (Intel, TSMC, and Samsung Electronics). This paper looks at the power-performance…”
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    Journal Article
  2. 2

    Creep characterization of solder bumps using nanoindentation by Du, Yingjie, Liu, Xiao Hu, Fu, Boshen, Shaw, Thomas M., Lu, Minhua, Wassick, Thomas A., Bonilla, Griselda, Lu, Hongbing

    Published in Mechanics of time-dependent materials (01-08-2017)
    “…Current nanoindentation techniques for the measurement of creep properties are applicable to viscoplastic materials with negligible elastic deformations. A new…”
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    Journal Article
  3. 3

    On the path to AI hardware via chiplet integration enabled by high density organic substrates by Bonilla, Griselda, Quinlan, Brian, Wassick, Thomas, Kastberg, Russell, Li, Shidong, Basutkar, Monali

    “…In this study, the heterogeneous integration of three mixed test chips is investigated and designed for AI hardware. An high bandwidth memory (HBM) test die, a…”
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    Conference Proceeding
  4. 4

    3-D Die Stacking With 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System by Sakuma, Katsuyuki, Farooq, Mukta, Andry, Paul, Cabral, Cyril, Wassick, Thomas, McHerron, Dale, Divakaruni, Rama

    “…In this letter, we have demonstrated a packaging technique for 3-D IC with Cu back-end-of-the line (BEOL) on a mixed pitch (55 and <inline-formula> <tex-math…”
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    Journal Article
  5. 5

    Finite Element Modeling of C4 Cracking in a Large Die Large Laminate Coreless Flip Chip Package by Shidong Li, Sinha, Tuhin, Wassick, Thomas A., Lombardi, Thomas E., Reynolds, Charles L., Quinlan, Brian W., Iruvanti, Sushumna

    “…BGA substrates made of organic materials are now industry standard as they provide significant advantages over the ceramic dielectric-based predecessors in…”
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    Conference Proceeding
  6. 6

    Reliable Chiplet Integration on High Density Laminate (2.XD) for AI Hardware by Taneja, Divya, Grenier, Jonathan, Ross, Joseph, Mori, Horiyuki, Raghvan, Sathya, Quinlan, Brian, De Sousa, Isabel, Wassick, Thomas, Bonilla, Griselda

    “…In this study, High Density Laminate with a bonded organic interposer (2.XD Laminate) is described and evaluated. The 2.XD laminate has <3 μm/3 μm L/S in the…”
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    Conference Proceeding
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    Direct Bonded Heterogeneous Integration (DBHi): Surface Bridge Approach for Die Tiling by Pulido, Claudia Cristina Barrera, Kohara, Sayuri, Jain, Aakrati, Wassick, Thomas, Taneja, Divya, McInnes, Philip, Horibe, Akihiro, De Sousa, Isabel

    “…With a continuous focus to maximize computational performance by optimizing package size and reducing fabrication costs, this paper presents the most recent…”
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    Conference Proceeding
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    Comparison of electromigration behaviors of SnAg and SnCu solders by Minhua Lu, Da-Yuan Shih, Goldsmith, C., Wassick, T.

    “…Two commonly used Pb-free solders, SnAg and SnCu, are studied for electromigration (EM) reliability. Two major EM failure mechanisms are identified in Sn-based…”
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    Conference Proceeding
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    Stress reduction methods within the Far Back End of Line (FBEOL) for fine pitch and 2.5D/3D packaging configurations by Tunga, Krishna, Wassick, Thomas, Guerin, Luc, Cournoyer, Maryse

    “…Fine pitch interconnects combined with 2.5D/3D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to…”
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    Conference Proceeding
  14. 14

    Inspection / Metrology Evaluation of Fine Pitch Test Vehicles for Advanced Packages by Xue, Feng, Zou, Joe, Han, Cindy, Reynolds, Charles, Wassick, Thomas, Pomerantz, Glenn, Frankel, Jason, Bonam, Ravi, Woychik, Charles, Tsuriya, Masahiro

    “…The demand for integrated silicon packages is driving packaging advancements for increasingly fine circuit pattern designs. Due to the thinner copper and finer…”
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    Conference Proceeding
  15. 15

    Chip-Package Interaction Challenges for Large Die Applications by Zhuo-Jie Wu, Carey, Charles, Donavan, Samantha, Hunt, Doug, Justison, Patrick, Anemikos, Theo, Cincotta, John, Gagnon, Hugues, Chacon, Oswaldo, Martel, Robert, Wassick, Thomas

    “…To enable higher computing power in a single chip, there is demand for increasing die size for high performance applications in advanced nodes. Due to the weak…”
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    Conference Proceeding
  16. 16

    Inspection/metrology benchmarking on fine pitch design substrate for advanced packages by Feng Xue, Watanabe, Hiroyuki, Han, Cindy, Reynolds, Charles, Wassick, Thomas, Pomerantz, Glenn, Tsuriya, Masahiro

    “…Integrated silicon packages, such as System in Package, are becoming more popular as electronic packaging solutions, and this technology is driving the need…”
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    Conference Proceeding
  17. 17

    Electromigration and thermal migration in Pb-free interconnects by Minhua Lu, Wassick, Thomas, Advocate, Gerald, Backes, Ben

    “…A set of experiments designed to understand the evolution of electromigration damage in Pb-free interconnects was conducted. It is found that the degree of EM…”
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    Conference Proceeding
  18. 18

    Effect of Ag and Cu content in Sn based Pb-free solder on electromigration by Minhua Lu, Goldsmith, Charles, Wassick, Thomas, Perfecto, Eric, Arvin, Charles

    “…The effect of Ag and Cu concentrations on the electromigration of Pb-free solder was investigated. A nine cell experiment with Ag concentrations ranging from…”
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    Conference Proceeding
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    Electrochemical reactions in solder mask of flip chip-plastic ball grid array package by Kang-Wook Lee, Barbeau, Stephane, Racicot, Francois, Powell, Douglas, Arvin, Charles, Wassick, Thomas, Ross, Joseph

    “…A typical flip chip plastic ball grid array (FC-PBGA) module utilizes a laminate substrate, which has a solder mask layer at the surface and a number of…”
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    Conference Proceeding
  20. 20

    Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology by Sakuma, K., Smith, K., Tunga, K., Perfecto, E., Wassick, T., Pompeo, F., Nah, J.

    “…A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to…”
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    Conference Proceeding