Search Results - "Waskiewicz, C."

Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning by Fan, S.-C., Jamison, P., Pancharatnam, S., Sankarapandian, M., Xie, R., Waskiewicz, C., Strane, J., Lee, J., Shobha, H., Demarest, J., Peethala, C., Jagannathan, H., Wynne, J.

“…Middle of Line (MOL) metallization with cobalt has been very promising to reduce the parasitic resistance of advanced CMOS devices. Though significant line…”
Get full text

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices by Jagannathan, H., Anderson, B., Sohn, C-W., Tsutsui, G., Strane, J., Xie, R., Fan, S., Kim, K-I., Song, S., Sieg, S., Seshadri, I., Mochizuki, S., Wang, J., Rahman, A., Cheon, K-Y., Hwang, I., Demarest, J., Do, J., Fullam, J., Jo, G., Hong, B., Jung, Y., Kim, M., Kim, S., Lallement, R., Levin, T., Li, J., Miller, E., Montanini, P., Pujari, R., Osborn, C., Sankarapandian, M., Son, G-H., Waskiewicz, C., Wu, H., Yim, J., Young, A., Zhang, C., Varghese, A., Robison, R., Burns, S., Zhao, K., Yamashita, T., Dechene, D., Guo, D., Divakaruni, R., Wu, T., Seo, K-I., Bu, H.

“…We demonstrate, for the first time, Vertical-Transport Nanosheet (VTFET) CMOS logic transistors at sub-45nm gate pitch on bulk silicon wafers. We show that…”
Get full text

Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology by Tsutsui, G., Song, S., Strane, J., Xie, R., Qin, L., Zhang, C., Schmidt, D., Fan, S., Hong, B., Jung, Y., Sohn, C-W., Hwang, I., Yim, J., Son, G. H., Jo, G., Kim, K-I., Sankarapandian, M., Mochizuki, S., Seshadri, I., Miller, E., Li, J., Demarest, J., Waskiewicz, C., Southwick, R. G., Zhou, H., Pujari, R. N., Nieves, P., Wang, M., Jagannathan, H., Anderson, B., Guo, D., Divakaruni, R., Wu, T., Seo, K-I., Bu, H.

“…Vertical-transport FET (VTFET) is a strong candidate for future CMOS technology. The concept of VTFET has been demonstrated in our previous report, which…”
Get full text

Introduction of an endocardial pacing lead through the costocervical vein in six dogs by Flanders, J A, Moïse, N S, Gelzer, A R, Waskiewicz, J C, MacGregor, J M

“…Lead dislodgement is one of the most common complications of endocardial pacing lead implantation in dogs. Incidence of lead displacement appears to be higher…”
Get more information

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI by Seo, K.-I, Haran, B., Gupta, D., Guo, D., Standaert, T., Xie, R., Shang, H., Alptekin, E., Bae, D.-I, Bae, G., Boye, C., Cai, H., Chanemougame, D., Chao, R., Cheng, K., Cho, J., Choi, K., Hamieh, B., Hong, J. G., Hook, T., Jang, L., Jung, J., Jung, R., Lee, D., Lherron, B., Kambhampati, R., Kim, B., Kim, H., Kim, K., Kim, T. S., Ko, S.-B, Lie, F. L., Liu, D., Mallela, H., Mclellan, E., Mehta, S., Montanini, P., Mottura, M., Nam, J., Nam, S., Nelson, F., Ok, I., Park, C., Park, Y., Paul, A., Prindle, C., Ramachandran, R., Sankarapandian, M., Sardesai, V., Scholze, A., Seo, S.-C, Shearer, J., Southwick, R., Sreenivasan, R., Stieg, S., Strane, J., Sun, X., Sung, M. G., Surisetty, C., Tsutsui, G., Tripathi, N., Vega, R., Waskiewicz, C., Weybright, M., Yeh, C.-C, Bu, H., Burns, S., Canaperi, D., Celik, M., Colburn, M., Jagannathan, H., Kanakasabaphthy, S., Kleemeier, W., Liebmann, L., Mcherron, D., Oldiges, P., Paruchuri, V., Spooner, T., Stathis, J., Divakaruni, R., Gow, T., Iacoponi, J., Jenq, J., Sampson, R., Khare, M.

“…A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and…”
Get full text

56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme by LOQUET, Yannick, MIGNOT, Yann, MORRIS, Bryan, KLEEMEIER, Walter, LINIGER, E, SPOONER, Terry, WASKIEWICZ, Christopher, CHEN, James Hsueh-Chung, SANKARAPANDIAN, Muthumanickam, CHEN, Shyng-Tsong, FLAITZ, Philip, TOMIZAWA, Hideyuki, TSENG, Chia-Hsun, BEARD, Marcy

“…In the attempts to push the resolution limits of 193 nm immersion lithography, this work demonstrates the building of 3 metal level 56 nm pitch copper…”
Get full text

Process-Induced Gate Oxide Damage Issues in Advanced Plasma Chemical Vapor Deposition Processes by Cote, D., Nguyen, S., Mcgahay, V., Waskiewicz, C., Chang, S., Stamper, A., Weigand, P., Shoda, N., Matsuda, T.

Get full text

56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme by Tagami, M., Shimada, K., Yin, Y., Ishikawa, M., Waskiewicz, C., Chen, S.-T, Shobha, H., Soda, E., Saulnier, N., Arnold, J. C., Colburn, M., Usui, T., Spooner, T.

“…Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme…”
Get full text

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via by Chen, J. H.-C, Waskiewicz, C., Fan, S. S.-C, Halle, S., Chiew-seng Koay, Yongan Xu, Saulnier, N., Chia-Hsun Tseng, Yunpeng Yin, Mignot, Y., Beard, M., Morris, B., Horak, D., Mignot, S., Shobha, H., Sankarapandian, M., van der Straten, O., Kelly, J. J., Canaperi, D., Mclellan, E., Boye, C., Levin, T., Juntao Li, Demarest, J., Choi, S., Huang, E., Liemann, L., Haran, B., Arnold, J. C., Colburn, M., Clevenger, L., Spooner, T.

“…This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0…”
Get full text