Search Results - "Walker, D.M.H."

Longest-path selection for delay test under process variation by Xiang Lu, Zhuo Li, Wangqi Qiu, Walker, D.M.H., Weiping Shi

“…Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay…”
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Estimation of fault-free leakage current using wafer-level spatial information by Sabade, S.S., Walker, D.M.H.

“…Leakage current or the I/sub DDQ/ test has been shown to be an effective test screen in combination with traditional test methods. However, leakage current is…”
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Static compaction of delay tests considering power supply noise by Jing Wang, Wangqi Qiu, Fancler, S., Walker, D.M.H., Xiang Lu, Ziding Yue, Weiping Shi

“…Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A…”
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Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits by Chakraborty, Avijit, Walker, D.M.H.

“…Delay test is used to verify the timing performance of integrated circuits. The test requires launching rising or falling transitions into the circuit and…”
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The essential role of test in DFM by Walker, D.M.H.

“…Design for manufacturing (DFM) is essential to achieving competitive yields in deep submicron technologies. The limiting factor in the successful application…”
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Dynamic Compaction for High Quality Delay Test by Zheng Wang, Walker, D.M.H.

“…Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic…”
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An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit by Wangqi Qiu, Walker, D.M.H.

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I/sub DDQ/ test using built-in current sensing of supply line voltage drop by Bin Xue, Walker, D.M.H.

“…A practical built-in current sensor (BICS) is described that senses the voltage drop on supply lines caused by quiescent current leakage. This noninvasive…”
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Challenges in Delay Testing of Integrated Circuits by Walker, D.M.H.

“…Delay testing of integrated circuits is increasingly focused on detecting small delay defects, and improving correlation to functional test. In this talk we…”
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On comparison of NCR effectiveness with a reduced I/sub DDQ/ vector set by Sabade, S., Walker, D.M.H.

“…I/sub DDQ/ test-based outlier rejection becomes difficult for deep sub-micron technology chips due to increased leakage and process variations. The use of…”
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K longest paths per gate (KLPG) test generation for scan-based sequential circuits by Qiu, W., Jing Wang, Walker, D.M.H., Reddy, D., Xiang Lu, Zhuo Li, Weiping Shi, Balachandran, H.

“…To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are…”
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A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations by Gulati, Kanupriya, Jayakumar, Nikhil, Khatri, Sunil P., Walker, D.M.H.

“…The control of leakage power consumption is a growing design challenge for current and future CMOS circuits. Among existing techniques, ‘parking’ a circuit in…”
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Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric by Zheng Wang, Walker, D.M.H.

“…This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a…”
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Immediate neighbor difference I/sub DDQ/ test (INDIT) for outlier identification by Sabade, S.S., Walker, D.M.H.

“…Increasing magnitude and variation in leakage current make it impossible to distinguish between faulty and fault-free chips using single threshold method…”
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Use of multiple I/sub DDQ/ test metrics for outlier identification by Sabade, S.S., Walker, D.M.H.

“…With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true…”
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Chip level power supply partitioning for I/sub DDQ/ testing using built-in current sensors by Prasad, A., Walker, D.M.H.

“…The International Technology Roadmap for Semiconductors projects that I/sub DDQ/ levels will rise rapidly with each technology node. In addition, manufacturing…”
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Neighbor current ratio (NCR): a new metric for I/sub DDQ/ data analysis by Sabade, S.S., Walker, D.M.H.

“…I/sub DDQ/ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault free currents. The concept of current…”
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A fast algorithm for critical path tracing in VLSI digital circuits by Lei Wu, Walker, D.M.H.

“…An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem…”
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IDDQ data analysis using neighbor current ratios by Sabade, Sagar S., Walker, D.M.H.

“…I DDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios,…”
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Improved wafer-level spatial analysis for I/sub DDQ/ limit setting by Sabade, S., Walker, D.M.H.

“…This paper proposes a new methodology for estimating the upper bound on the I/sub DDQ/ of defect free chips by using wafer level spatial information. This can…”
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