Search Results - "WALSTRA, Steven"

EXTENSION OF THE McNUTT-SAH METHOD FOR MEASURING THIN OXIDE THICKNESSES OF MOS DEVICES by Walstra, Steven V., Sah, Chih-Tang

“…Oxide capacitance and thickness are critical parameters in MOS process monitoring and device modeling. For process monitoring, where rapid results and minimum…”
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Effect of intrinsic capacitance degradation on circuit performance by Dai, Changhong, Walstra, Steven V, Lee, Shiuh-Wuu

“…The effect of intrinsic capacitance degradation on circuit performance has been investigated. Results show that: (1) the measured C sub(gd) decreases while C…”
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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, B A, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, G E, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
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Frequency and recovery effects in high-κ BTI degradation by Ramey, S., Prasad, C., Agostinelli, M., Sangwoo Pae, Walstra, S., Gupta, S., Hicks, J.

“…Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is…”
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Thin oxide thickness extrapolation from capacitance-voltage measurements by Walstra, S.V., Chih-Tang Sah

“…Five oxide-thickness extrapolation algorithms, all based on the same model (metal gate, negligible interface traps, no quantum effects), are compared to…”
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Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process by HAZUCHA, Peter, KARNIK, Tanay, BORKAR, Shekhar, WALSTRA, Steven, BLOECHEL, Bradley A, TSCHANZ, James W, MAIZ, Jose, SOUMYANATH, Krishnamurthy, DERMER, Gregory E, NARENDRA, Siva, DE, Vivek

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EXTENSION OF THE M cNUTT-SAH METHOD FOR MEASURING THIN OXIDE THICKNESSES OF MOS DEVICES by Walstra, Steven V., Sah, Chih-Tang

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Scaling effects on metal-oxide-semiconductor device characteristics by Walstra, Steven Vincent

“…As metal-oxide-semiconductor (MOS) transistor dimensions are decreased, channel-length modulation, polysilicon-gate depletion, and intrinsic-capacitance…”
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Circuit-level modeling of soft errors in integrated circuits by Walstra, S.V., Changhong Dai

“…This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error…”
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