Search Results - "Vitiello, Julien"

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    Investigation of different methods for isolation in through silicon via for 3D integration

    Investigation of different methods for isolation in through silicon via for 3D integration by Sage, Stéphane, John, Peggy, Dobritz, Stephan, Börnge, Jochen, Vitiello, Julien, Böttcher, Matthias

    Published in Microelectronic engineering (01-07-2013)
    “…[Display omitted] ► SiO2 dielectric layers were deposited in 10:1 aspect ratio TSVs at low temperatures. ► Deposition was performed in a 300mm AltaCVD©…”
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    Journal Article Conference Proceeding
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  2. 2
    Alternative Deposition Solution for Cost Reduction of TSV Integration

    Alternative Deposition Solution for Cost Reduction of TSV Integration by Vitiello, Julien, Piallat, Fabien

    “…As one of the key enabler of 3D integration, Through Silicon Via (TSV) was widely investigated but not largely adopted in the advanced packaging industry. TSV…”
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    Impact of dielectric stack and interface adhesion on mechanical properties of porous ultra low- k

    Impact of dielectric stack and interface adhesion on mechanical properties of porous ultra low- k by Vitiello, Julien, Fuchsmann, Arno, Chapelon, Laurent-Luc, Arnal, Vincent, Barbier, Daniel, Torres, Joaquin

    Published in Microelectronic engineering (01-12-2005)
    “…Introduced for next interconnect generations to replace dense low- k materials, porous dielectrics exhibit poor mechanical properties, which are difficult to…”
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