Search Results - "Verrun, Sophie"

High pass filter with above IC integrated SrTiO3 high K MIM capacitors by DELAY, Emmanuel, WOLOZAN, David, ULMER, Laurent, AÏD, Marc, ANCEY, Pascal, BLANC, Jean-Pierre, SERRET, Emmanuelle, GARREC, Pierre, VERRUN, Sophie, PELLISSIER, Denis, DELPECH, Philippe, GUILLAN, Julie, ANDRE, Bernard

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High pass filter with above IC integrated SrTiO 3 high K MIM capacitors by Defaÿ, Emmanuel, Wolozan, David, Blanc, Jean-Pierre, Serret, Emmanuelle, Garrec, Pierre, Verrun, Sophie, Pellissier, Denis, Delpech, Philippe, Guillan, Julie, André, Bernard, Ulmer, Laurent, Aïd, Marc, Ancey, Pascal

“…This paper describes realization and characterization of SrTiO 3 (STO) high K MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are…”
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Ultra Wide Micro Bumps Interconnection Matrix for High Energy Particle Detection: Process and Assembly by Charbonnier, Jean, Assous, Myriam, Mourier, Thierry, Ribiere, Celine, Minoret, Stephane, Verrun, Sophie, Tissier, Pierre, Coquand, Remi, Bicer, Mehmet, Allain, Fabienne, Franiatte, Remi, Pares, Gabriel

“…Micro pillars and micro bumps interconnections are considered as mature technology for 3-D integration and chip stacking. However, in the framework of…”
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Reliability tests on micro-insert die bonding technology by Nowodzinski, A., Boutry, H., Franiatte, R., Mandrillon, V., Anciant, R., Verrun, S., Simon, G.

“…Micro-insert technology is a wafer level stacking technology offering main advantages such as simplicity, low cost and compatibility with chip assembly…”
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First integration of Cu TSV using die-to-wafer direct bonding and planarization by Leduc, P., Assous, M., Di Cioccio, L., Zussy, M., Signamarcheix, T., Roman, A., Rousseau, M., Verrun, S., Bally, L., Bouchu, D., Cadix, L., Farcy, A., Sillon, N.

“…Copper-filled Through-Si Vias (TSV) with diameters from 2 mum to 5 mum have been integrated in a die-to-wafer stack combining direct bonding and a…”
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An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling by Di Cioccio, L., Gueguen, P., Taibi, R., Signamarcheix, T., Bally, L., Vandroux, L., Zussy, M., Verrun, S., Dechamp, J., Leduc, P., Assous, M., Bouchu, D., de Crecy, F., Chapelon, L.-L., Clavelier, L.

“…An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or…”
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