Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA

Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA

Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their use in real-time applications. This paper presents a fully scalable architecture of a coprocessor, which can compute multiple rows of the kerne...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 10; pp. 2221 - 2232
Main Authors: Venkateshan, Sriram, Patel, Alap, Varghese, Kuruvilla
Format: Journal Article
Language:English
Published: New York IEEE 01-10-2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Cache
Convergence
Coprocessors
FPGA
hardware-software codesign
hybrid working set (HWS)
Kernel
Random access memory
Semiconductors
sequential minimal optimization (SMO)
support vector machine (SVM)
Support vector machines
Training
Vectors
sequential minimal optimization (SMO)
hardware–software codesign
hybrid working set (HWS)
FPGA
support vector machine (SVM)
Cache
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their use in real-time applications. This paper presents a fully scalable architecture of a coprocessor, which can compute multiple rows of the kernel matrix in parallel. Further, we propose an extended variant of the popular decomposition technique, sequential minimal optimization, which we call hybrid working set (HWS) algorithm, to effectively utilize the benefits of cached kernel columns and the parallel computational power of the coprocessor. The coprocessor is implemented on Xilinx Virtex 7 field-programmable gate array-based VC707 board and achieves a speedup of up to 25× for kernel computation over single threaded computation on Intel Core i5. An application speedup of up to 15× over software implementation of LIBSVM and speedup of upto 23× over SVMLight is achieved using the HWS algorithm in unison with the coprocessor. The reduction in the number of iterations and sensitivity of the optimization time to variation in cache size using the HWS algorithm are also shown.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2014.2361254