Search Results - "Veneris, A."

Fault diagnosis and logic debugging using Boolean satisfiability by Smith, A., Veneris, A., Ali, M.F., Viglas, A.

“…Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scale-integration design problems. Although…”
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Automated Design Debugging With Abstraction and Refinement by Safarpour, S., Veneris, A.

“…Design debugging is one of the major remaining manual processes in the semiconductor design cycle. Despite recent advances in the area of automated design…”
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Incremental fault diagnosis by Liu, J.B., Veneris, A.

“…Fault diagnosis is important in improving the circuit-design process and the manufacturing yield. Diagnosis of today's complex defects is a challenging problem…”
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L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture by Safi, E., Moshovos, A., Veneris, A.

“…An increasing number of architectural techniques have relied on hardware counting bloom filters (CBFs) to improve upon the energy, delay, and complexity of…”
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Design error diagnosis and correction via test vector simulation by Veneris, A., Hajj, I.N.

“…With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector…”
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Design rewiring using ATPG by Veneris, A., Abadir, M.S.

“…Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy…”
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Extraction error modeling and automated model debugging in high-performance custom designs by Yu-Shen Yang, Veneris, A., Thadikaran, P., Venkataraman, S.

“…In the design cycle of high-performance integrated circuits, it is common that certain components are designed directly at the transistor level. This level of…”
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Managing don't cares in Boolean satisfiability by Safarpour, S., Veneris, A., Drechsler, R., Lee, J.

“…Advances in Boolean satisfiability solvers have popularized their use in many of today's CAD VLSI challenges. Existing satisfiability solvers operate on a…”
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Path-Directed Abstraction and Refinement for SAT-Based Design Debugging by Keng, B., Veneris, A.

“…Functional verification has become one of the most time-consuming tasks in the very large scale integration design flow accounting for up to 57% of the total…”
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Incremental diagnosis of multiple open-interconnects by Liu, J.B., Veneris, A., Takahashi, H.

“…With increasing chip interconnect distances, open-interconnect is becoming an important defect. The main challenge with open-interconnects stems from its…”
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Fault diagnosis and logic debugging using Boolean satisfiability by Veneris, A.

“…Recent advances in Boolean satisfiability have made it attractive to solve many digital VLSI design problems such as verification and test generation. Fault…”
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Incremental diagnosis and correction of multiple faults and errors by Veneris, A., Liu, J.B., Amiri, M., Abadir, M.S.

“…An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious…”
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Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs by Yang, Yu-Shen, Veneris, Andreas, Thadikaran, Paul, Venkataraman, Srikanth

“…Test model generation is common in the design cycle of custom made high performance low power designs targeted for high volume production. Logic extraction is…”
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Extraction error diagnosis and correction in high-performance designs by Yu-Shen Yang, Liul, J.B., Thadikaran, P., Veneris, A.

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Design rewiring using ATPG by Veneris, A., Abadir, M.S., Amiri, M.

“…Technology dependent logic optimization is usually carried through a sequence of design rewiring operations. In Veneris et al (Proc. Asian-South-Pacific Design…”
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Design diagnosis using Boolean satisfiability by Smith, A., Veneris, A., Viglas, A.

“…Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital VLSI design problems such as verification, model checking,…”
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Two-Stage, Pipelined Register Renaming by Safi, E., Moshovos, A., Veneris, A.

“…Register renaming is a performance-critical component of modern, dynamically-scheduled processors. Register renaming latency increases as a function of several…”
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Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability by Mangassarian, H., Veneris, A., Najm, F. N.

“…With lower supply voltages, increased integration densities and higher operating frequencies, power grid verification has become a crucial step in the very…”
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Post-verification debugging of hierarchical designs by Ali, M.F., Safarpour, S., Veneris, A., Abadir, M.S., Drechsler, R.

“…As VLSI designs grow in complexity and size, errors become more frequent and difficult to track. Recent developments have automated most of the verification…”
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Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment by Yu-Shen Yang, Veneris, A., Nicolici, N.

“…With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in…”
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