Search Results - "Velez, Sorono Dexter"

Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip-Embedded Wafer Level Packages by Ho Siow Ling, Bu Lin, Chong Ser Choong, Velez, Sorono Dexter, Chai Tai Chong, Xiaowu Zhang

“…Comprehensive numerical and experimental analyses were performed to investigate the issue of die shift during the 12-in wafer level molding process of…”
Get full text

Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer by Lim, Sharon Pei-Siang, Mian Zhi Ding, Velez Sorono, Dexter, Cereno, Daniel Ismael, Jong Kai Lin, Rao, Vempati Srinivasa

“…The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption…”
Get full text

Optimization of the wafer level molding process for high power device module by Lin Bu, Siow Ling Ho, Velez Sorono, Dexter, Woo, Daniel Rhee Min

“…High power modules are indispensible in our future automotive, aerospace and green & renewable energy industry. However, a lot of issues rise along with the…”
Get full text

Thermo-mechanical reliability study on Package on Package (PoP) with Embedded Wafer Level Package (eWLP) by Chen, Zhaohui, Jung, Boo Yang, Lim, Sharon Pei Siang, Velez, Dexter Sorono, Ho, David Soon Wee, Zhang, Xiaowu

“…In order to improve the reliability of the proposed test vehicle of the Package on Package (PoP) with Embedded Wafer Level Package (eWLP) using through mold…”
Get full text

Development of SiC power module using 70μm single metal layer substrates by Hwang How Yuan, Jaafar, Norhanani, Dexter Velez, Sorono, Lee Jong Bum, Yeap Yean Wei, Woo, Daniel Rhee Min

“…While leadframe has come a long way as a cost effective substrate, there is still limitation over its design rule. In this article, the authors have developed…”
Get full text

Simultaneous molding and under-filling for void free process to encapsulate fine pitch micro bump interconnections of chip-to-wafer (C2W) bonding in wafer level packaging by Velez Sorono, Dexter, Vempati, Srinivasa Rao, Lin Bu, Ser Choong Chong, Liang, Calvin Teo Wei, Seit Wen Wei

“…The encapsulation of chips with fine pitch micro bump interconnections in chip-to-wafer (C2W) bonding has a known two steps process in wafer level packaging…”
Get full text

Novel high performance millimeter-wave resonator and filter structures using embedded wafer level packaging (EWLP) technology by Rui Li, Boo Yang Jung, Cheng Jin, Chang Ka Fai, Soon Wee Ho, Velez Sorono, Dexter

“…In this paper, a 60 GHz resonator is designed and implemented on embedded wafer level packaging (EWLP) platform. The resonator is constructed in substrate…”
Get full text

Investigation on Die Shift Issues in the 12-in Wafer-Level Compression Molding Process by Lin Bu, Siowling Ho, Velez, Sorono Dexter, Taichong Chai, Xiaowu Zhang

“…Die shift issues that arise in embedded wafer-level packaging because of the mold flow process is investigated in this paper, along with solution strategies to…”
Get full text

3-D Numerical and Experimental Investigations on Compression Molding in Multichip Embedded Wafer Level Packaging by Lin Ji, Sorono, D. V., Tai Chong Chai, Xiaowu Zhang

“…This paper focuses on the 3-D numerical methodology development of wafer level compression molding. With its successful application in a two-die-package…”
Get full text

Design and Optimization of Wafer-Level Compression Molding Process for One Chip Plus Multiple Decaps by Lin Bu, Siowling Ho, Velez, Sorono Dexter, Lau Boon Long, Booyang Jung, Taichong Chai, Xiaowu Zhang

“…Decaps are the panacea for the noise-related issues. Due to the short distance advantage, decaps are embedded in the fan-out wafer-level package instead of the…”
Get full text

High power SiC inverter module packaging solutions for junction temperature over 220°C by Woo, Daniel Rhee Min, Hwang How Yuan, Li, Jerry Aw Jie, Ho Siow Ling, Lee Jong Bum, Zhang Songbai, Zhang Hengyun, Selvaraj, Susai Lawrence, Velez, Sorono Dexter, Singh, Ravinder Pal

“…The SiC based high power 3 phase inverter module with double side cooling structure was developed. By applying flipchip bonding of SiC based high power DMOSFET…”
Get full text

Development of low profile fan out PoP solution with embedded passive by Jung, Boo Yang, Ho, David Soon Wee, Sorono, Dexter Velez, Lim, Sharon Pei Siang, Chen, Zhaohui, Yong, Han, Lin, Bu, Chong, Chai Tai

“…Currently PoP (Package on Package) has become a main stream of 3D integration for logic devices such as baseband and application processors with high…”
Get full text

Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer by Pei-Siang, Sharon Lim, Ding, L., MingBin Yu, Mian Zhi Ding, Dexter Velez, Sorono, Rao, Vempati Srinivasa

“…The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption…”
Get full text

Study on mold flow during compression molding for embedded wafer level package (EMWLP) with multiple chips by Sorono, D. V., Ji Lin, Chai Tai Chong, Ser Choong Chong, Vempati, S. R.

“…The rapidly increasing demand of embedded wafer level package (EMWLP) due to its advantages, smaller form factor and flexibility in system level integration…”
Get full text

Investigation on decap shift and incomplete fill issues in the wafer level compression molding process by Lin Bu, Siowling Ho, Dexter Velez, Sorono, Boyu Zheng, Ser Choong Chong, Booyang Jung, Taichong Chai, Xiaowu Zhang

“…Decaps are the panacea to cure the noise related issues. Due to the short distance advantage, decaps were embedded in the package instead of PCB. These decaps,…”
Get full text