Search Results - "Varghese, Kuruvilla"

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  1. 1

    Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network by Shah, Nimish, Chaudhari, Paragkumar, Varghese, Kuruvilla

    “…The deep convolutional neural network (DCNN) is a class of machine learning algorithms based on feed-forward artificial neural network and is widely used for…”
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    Journal Article
  2. 2

    Network Emulation For Tele-driving Application Development by Acharya, Srikrishna, Sadgun S Devanahalli, S, Rawat, Alok, Kuruvilla, Varghese P, Sharma, Pratik, Amrutur, Bharadwaj, Joglekar, Ashish, Krishnapuram, Raghu, Simmhan, Yogesh, Tyagi, Himanshu

    “…We present a co-emulation framework for Connected Autonomous Vehicle for development and validation of technologies for teleoperation of semi-autonomous…”
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    Conference Proceeding
  3. 3

    Endovascular management of hemoptysis in a known case of tetralogy of fallot and tuberculosis complicated with aspergilloma: a case report by Varghese, Jerin Kuruvilla, Agarwal, Vivek, Batra, Amit

    “…Background Hemoptysis is a life-threatening complication due to bleeding either from hypertrophied bronchial arteries or enlarged non-bronchial systemic…”
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    Journal Article
  4. 4

    Multiparametric Measurements of the Eustachian tube and Peritubal Region Using Computed Tomography as a Preoperative Workup for Tuboplasty by Varghese, Jerin Kuruvilla, George, Uttam B, Varghese, Ashish

    “…Background Eustachian tube dysfunction (ETD) is considered a causative factor for middle ear disease as well as treatment failure. The pathogenesis may be a…”
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    Journal Article
  5. 5

    High-Level Synthesis of Geant4 Particle Transport Application for FPGA by Joshi, Ramakant, Varghese, Kuruvilla

    “…Geant4 is a software toolkit that simulates particle transport in matter and is widely used in high energy, nuclear, and medical physics applications. As…”
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    Conference Proceeding
  6. 6

    A Soft RISC-V Vector Processor for Edge-AI by Chander, V. Naveen, Varghese, Kuruvilla

    “…Edge computing is the key to unlocking the power of deep neural networks on edge devices. However, deploying power-hungry deep neural network inference on…”
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    Conference Proceeding
  7. 7

    Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA by Venkateshan, Sriram, Patel, Alap, Varghese, Kuruvilla

    “…Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their…”
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    Journal Article
  8. 8

    Hardware Accelerator for Capsule Network based Reinforcement Learning by Ram, Dola, Panwar, Suraj, Varghese, Kuruvilla

    “…Convolutional neural networks are widely used in reinforcement learning. Capsule networks are gaining popularity over the traditional convolutional neural…”
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    Conference Proceeding
  9. 9

    Accelerating method of moments based package-board 3D parasitic extraction using FPGA by Devi, Anant, Gandhi, Maulik, Varghese, Kuruvilla, Gope, Dipanjan

    Published in Microwave and optical technology letters (01-04-2016)
    “…ABSTRACT In this article, a Field Programmable Gate Array (FPGA)‐based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is…”
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    Journal Article
  10. 10

    A Scalable High Throughput Firewall in FPGA by Jedhe, G.S., Ramamoorthy, A., Varghese, K.

    “…High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands…”
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    Conference Proceeding
  11. 11

    Dynamically reconfigurable regular expression matching architecture by Divyasree, J., Rajashekar, H., Varghese, K.

    “…Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching…”
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    Conference Proceeding
  12. 12

    Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core by S, Sajin, Garag, Shubham Sunil, Phegade, Anuj, Gusain, Deepshikha, Varghese, Kuruvilla

    “…We present the design of a 64-bit Out-of-Order Superscalar processor core based on open-source RISC-V instruction set architecture. It implements RV64IMAFDC…”
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    Conference Proceeding
  13. 13

    The spectrum of radiological findings of rhino orbital cerebral mucormycosis with endoscopic and histopathological features in patients with COVID 19: A descriptive study by Susan, Anjali, Varghese, Jerin, Agarwal, Vivek, Bhatia, Dimple, Singla, Subhash, Varghese, Ashish, Paul, Preethi

    Published in Nigerian journal of medicine (01-11-2022)
    “…Background: There had been an increasing incidence of mucormycosis during the COVID-19 pandemic. Aim: This study evaluates the pattern of radiological imaging,…”
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    Journal Article
  14. 14

    A high-throughput clock-less architecture for soft-output Viterbi detection by Dey, Arnab, Jose, Sebin, Varghese, Kuruvilla, Srinivasa, Shayan Garani

    “…Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect…”
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    Conference Proceeding
  15. 15

    A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA by Datta, Saugata, Varghese, Kuruvilla, Srinivasa, Shayan Garani

    “…Soft output Viterbi detectors (SOVA) are universally used in all communication receivers within the digital back-end circuitry for mitigating intersymbol…”
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    Conference Proceeding Journal Article
  16. 16

    Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder by Ram, Sadhu Sai, Varghese, Kuruvilla

    “…Posit arithmetic, an alternative to IEEE 754 f1oating-point arithmetic, offers higher precision and a wider dynamic range. In posit, the number of bits…”
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    Conference Proceeding
  17. 17

    Synchronization Support in 64-bit Out-Of-Order Superscalar Dual-Core RISC-V Processor by Yadav, Shubham, Kumar, Manish, S, Sajin, Garag, Shubham Sunil, Varghese, Kuruvilla

    “…This paper discusses the implementation of atomic instructions in a dual-core 64-bit out-of-order superscalar processors based on the open-source RISC-V…”
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    Conference Proceeding
  18. 18

    High Throughput Hardware Acceleration for Image Generation using HLS by Prasad, A Bhanu, Varghese, Kuruvilla

    “…New machine learning techniques have been developed and used to generate new data in recent years. Genera-tive adversarial networks is a neural network model…”
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    Conference Proceeding
  19. 19

    High Throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor by Antony, Ashin, A, Devi, Varghese, Kuruvilla

    “…Hoeffding tree algorithm is a popular online decision tree algorithm capable of learning from huge data streams. The algorithm involves complex time consuming…”
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    Conference Proceeding
  20. 20

    An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment by S, Ajay, V S, Praveen, Varghese, Kuruvilla

    “…Advances in next-generation sequencing technolo-gies have resulted in a prodigious amount of genomic sequence data. Harnessing the information encoded in a…”
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    Conference Proceeding