An Efficient SRAM-Based Ternary Content Addressable Memory (TCAM) with Soft Error Correction

Ternary Content Addressable Memory (TCAM) is a high-speed memory that is extensively used in high-speed search applications like network routers. The TCAM architecture implemented in ASIC (Application Specific Integrated Circuits) provides a faster search rate but consumes more power and uses more r...

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Bibliographic Details
Published in:	2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) pp. 1 - 6
Main Authors:	Varada, Anwesh, Agrawal, Sonali
Format:	Conference Proceeding
Language:	English
Published:	IEEE 24-09-2021
Subjects:	2D parity Application Specific Integrated Circuit (ASIC) Application specific integrated circuits Associative memory Delays Error correction multi-pumping Multiplexing Performance analysis Random access memory soft Error Static Random-Access Memory (SRAM) Ternary Content Addressable Memory (TCAM)
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Summary:	Ternary Content Addressable Memory (TCAM) is a high-speed memory that is extensively used in high-speed search applications like network routers. The TCAM architecture implemented in ASIC (Application Specific Integrated Circuits) provides a faster search rate but consumes more power and uses more resources. For the effective utilization of resources and for reducing power, TCAM with a multi-pumping technique is designed. When TCAM is implemented in ASIC, another generally faced challenge is that they are prone to soft errors. Due to the shrinking of technology nodes, TCAM implementation is more vulnerable to soft errors. So, error correction techniques must be applied to protect the TCAM. This paper proposes a novel power-efficient multi-pumping enabled TCAM design with multi-bit error detection and correction capacity. The proposed TCAM is designed by replacing the priority encoder in the existing design with multiplexers and the error correction is carried by using the 2D parity technique. The proposed TCAM architecture with various sizes like 4 x 4, 16 x 8, 512 x 28, and 1024 x 40, is coded in Verilog HDL, simulated using Xilinx ISE, and its performance is compared with the existing TCAM architecture using Cadence Genus synthesis solution in 45nm technology. The performance analysis shows that the proposed TCAM architecture has achieved improved performance in terms of power and area. In the proposed TCAM with multi-pumping factor 4 and 2D parity error correction technique, the number of bits that can be corrected has become four times with improved area, power, and speed performances as compared to existing TCAM [13].
ISSN:	2767-9934
DOI:	10.1109/IEMENTech53263.2021.9614696