Search Results - "Vangal, S.R."

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS by Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.

“…This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched…”
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A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization by Vangal, S.R., Hoskote, Y.V., Borkar, N.Y., Alvandpour, A.

“…A pipelined single-precision floating-point multiply-accumulator (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save…”
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