Search Results - "Van Noije, W.A.M."

The sPHENIX Micromegas Outer Tracker by Aune, S., Azmoun, B., Bonenfant, A., Boose, S., Bregant, M., Cacace, D., da Silva, R.W., Feder, R., Francisco, A., Goblin, C., Grabas, A., Haggerty, J.S., Hernandez, R.A., Herrera, H.D.H., Huang, J., Kelsey, J., Kotov, I., Kuczewski, J., Mandjavidze, I., Martins, T.A., Mead, J., Mills, J., Oskarsson, A., Da Costa, H. Pereira, Pinkenburg, C., Pisani, R., Protzman, T., Purschke, M.L., Renner, E., Ruggiero, R., Sakaguchi, T., Sanches, B.C.S., Sayki, B., Silvermyr, D., Sondheim, W., Vandenbroucke, M., Van Noije, W.A.M., Vasquez, J., Vidal, C., Wils, A.

“…The sPHENIX Time Projection Chamber Outer Tracker (TPOT) is a Micromegas based detector. It is a part of the sPHENIX experiment that aims to facilitate the…”
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Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design by Joao Navarro, S., Van Noije, W.A.M.

“…New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock…”
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Precise final state determination of mismatched CMOS latches by Van Noije, W.A.M., Liu, W.T., Navarro, S.J.

“…The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small…”
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A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) by Navarro Soares, J., Van Noije, W.A.M.

“…The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC…”
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Mismatch effect analyses in CMOS tapered buffers by Aragao, A.J., Navarro, J., Van Noije, W.A.M.

“…A study of delay deviation in CMOS tapered buffers due to transistor mismatching is presented. Theoretical relations for the delay deviation were derived from…”
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Initiatives for promotion of microelectronics and microfabrication at Sao Paulo State Universities-Brazil by Van Noije, W.A.M., Swart, J.W., Seabra, A.C., Verdonck, I., Zambom, L.S., Diniz, J.A., Doi, I., Zakia, M.B.P., Mansano, R.D., Moreira, L.

“…This paper describes the five most important initiatives taken by Sao Paulo State Universities in Brazil to promote microelectronic and microfabrication…”
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A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution by Gray, C.T., Wentai Liu, Van Noije, W.A.M., Hughes, T.A., Cavin, R.K.

“…This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously…”
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A pulse generator UWB-Ultra Wide Band using PFD Phase Frequency Detector in 180nm CMOS technology by Moreira, L.C., Van Noije, W.A.M., Dionisio, C.R.P., Ascama, H.D.O., Kofuji, S.T.

“…This paper presents a design of a transmitter pulse generator UWB-Ultra Wide Band in standard 180 nm MOSIS/CMOS technology. We proposed a pulse generator using…”
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Design of an 8:1 MUX at 1.7 Gbit/s in 0.8 /spl mu/m CMOS technology by Navarro, J., Van Noije, W.A.M.

“…The design of an 8:1 multiplexer circuit, for SDH/SONET data transmission systems, is presented. In order to achieve maximum transmission rates, new circuits,…”
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A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology by de Miranda, F.P.H., Navarro, S.J., Van Noije, W.A.M.

“…The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency…”
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Small area cross type integrated inductor in CMOS Technology by Moreira, L.C., Van Noije, W.A.M., Farfan-Pelaez, A., dos Anjos, A.

“…This paper describes the design and simulation, using the SONNET tool, of a new inductor structure with crossed segments (cross). In order to compare, the new…”
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Modeling an E1/TU12 mapper for SDH systems by Silveira, R., Van Noije, W.A.M.

“…The mapping problem of PDH signals into SDH systems is analyzed. Plesiochronous Digital Hierarchy (PDH) is a quasi-synchronous system used for multiplexing and…”
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Metastability behavior of mismatched CMOS flip-flops using state diagram analysis by van Noije, W.A.M., Liu, W.T., Navarro, J.

“…The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state…”
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A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems by Navarro S., J., Silveira, R., Romao, F.L., Van Noije, W.A.M.

“…This paper presents an output buffer which converts CMOS into ECL levels, and a brief analysis of its speed performance. The structure is designed in a 0.8…”
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The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput by Navarro S., J., Van Noije, W.A.M.

“…New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional TSPC, are presented…”
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A simple RISC microprocessor core designed for digital set-top-box applications by Dal Poz, M.A.S., Aedo Cobo, J.E., Van Noije, W.A.M., Zuffo, M.K.

“…We propose the definition and evaluation of an instruction set designed and tuned for multimedia applications on a digital set-top-box. The proposed…”
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Advanced CMOS gate array architecture combining `gate isolation' and programmable routing channels by Van Noije, W.A.M., Declerck, G.J.

“…A description is given of a novel CMOS gate array architecture for LSI/VLSI complexity. The new structure is based on the `gate isolation' technique for logic…”
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VHDL models for high level synthesis of fuzzy logic controllers by Cobo, J.E.A., Van Noije, W.A.M., Gualberto, L.

“…This paper defines a set of the architectural models for implementation of fuzzy logic controllers (FLC) in hardware. These models are defined in order to…”
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CMOS tapered buffer design for small width clock/data signal propagation by Navarro, J., Van Noije, W.A.M.

“…A new optimization criterion, the propagation of the minimum width pulse through the buffer is studied for design of tapered buffers draining capacitive loads…”
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Prototyping a pager-like device using FPGAs: design of an object finder by Cerezo Vasquez, G.A., Van Noije, W.A.M., Barbin, S.E.

“…The use of Field Programmable Gate Array (FPGA) devices for designing and prototyping a pager-like device is presented. The device executes the decoding tasks…”
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