Search Results - "Van Dal, Mark J.H."

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping by van Dal, Mark J. H., Vellianitis, Georgios, Duriez, Blandine, Doornbos, Gerben, Chih-Hua Hsieh, Bi-Hui Lee, Kai-Min Yin, Passlack, Matthias, Diaz, Carlos H.

“…We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a…”
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Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization by van Dal, Mark J. H., Duriez, Blandine, Vellianitis, Georgios, Doornbos, Gerben, Passlack, Matthias, Yee-Chia Yeo, Diaz, Carlos H.

“…We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density D it below 2 × 10…”
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High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates by Doornbos, Gerben, Holland, Martin, Vellianitis, Georgios, Van Dal, Mark J. H., Duriez, Blandine, Oxland, Richard, Afzalian, Aryan, Ta-Kun Chen, Hsieh, Gordon, Passlack, Matthias, Yee-Chia Yeo

“…We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration…”
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Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations by Conzatti, F, Serra, N, Esseni, D, De Michielis, M, Paussa, A, Palestri, P, Selmi, L, Thomas, S M, Whall, T E, Leadley, D, Parker, E H C, Witters, L, Hytch, M J, Snoeck, E, Wang, T J, Lee, W C, Doornbos, G, Vellianitis, G, van Dal, M J H, Lander, R J P

“…This study combines direct measurements of strain, electrical mobility measurements, and a rigorous modeling approach to provide insights about strain-induced…”
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Evaluation of Transmission Line Model Structures for Silicide-to-Silicon Specific Contact Resistance Extraction by Stavitski, N., van Dal, M.J.H., Lauwers, A., Vrancken, C., Kovalgin, A.Y., Wolters, R.A.M.

“…In order to measure silicide-to-silicon specific contact resistance rho c , transmission line model (TLM) structures were proposed as attractive candidates for…”
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Ni based silicides for 45 nm CMOS and beyond by Lauwers, Anne, Kittl, Jorge A., Van Dal, Mark J.H., Chamirian, Oxana, Pawlak, Malgorzata A., de Potter, Muriel, Lindsay, Richard, Raymakers, Toon, Pages, Xavier, Mebarki, Bencherki, Mandrekar, Tushar, Maex, Karen

“…Material issues that impact the applicability of Ni based silicides to CMOS flows were studied, including the excessive silicidation of narrow features, the…”
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Ni fully silicided gates for 45 nm CMOS applications by Kittl, Jorge A., Lauwers, Anne, Pawlak, Malgorzata A., van Dal, Mark J.H., Veloso, Anabela, Anil, K.G., Pourtois, Geoffrey, Demeurisse, Caroline, Schram, Tom, Brijs, Bert, de Potter, Muriel, Vrancken, Christa, Maex, Karen

“…The Ni silicide phases and morphology in Ni fully silicided gates was investigated for varying deposited Ni to Si thickness ratios and rapid thermal processing…”
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Demonstration of short-channel self-aligned Pt2Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON by VAN DAL, M. J. H, BOCCARDI, G, VELOSO, A, LOCOROTONDO, S, SHI, X, DEMEURISSE, C, VRANCKEN, C, VERBEECK, R, LAUWERS, A, KITTL, J. A

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Effect of SIIS on work function of self-aligned PtSi FUSI metal-gated capacitors by van Dal, M.J.H., Pourtois, G., Cunniffe, J., Veloso, A., Lauwers, A., Maex, K., Kittl, J.A.

“…A novel self-aligned fully silicided (FUSI) gate process for the integration of platinum monosilicide (PtSi) as a metal gate for pMOS applications is…”
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Germanium-based transistors for future high performance and low power logic applications by Yee-Chia Yeo, Xiao Gong, van Dal, Mark J. H., Vellianitis, Georgios, Passlack, Matthias

“…High mobility channel materials could replace strained Si to enhance speed performance and/or reduce power consumption in future transistors. Ge has the…”
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Ni based silicides for 45nm CMOS and beyond by Lauwers, Anne, Kittl, Jorge A., Van Dal, Mark J.H., Chamirian, Oxana, Pawlak, Malgorzata A., de Potter, Muriel, Lindsay, Richard, Raymakers, Toon, Pages, Xavier, Mebarki, Bencherki, Mandrekar, Tushar, Maex, Karen

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Ni fully silicided gates for 45nm CMOS applications by Kittl, Jorge A., Lauwers, Anne, Pawlak, Malgorzata A., van Dal, Mark J.H., Veloso, Anabela, Anil, K.G., Pourtois, Geoffrey, Demeurisse, Caroline, Schram, Tom, Brijs, Bert, de Potter, Muriel, Vrancken, Christa, Maex, Karen

“…The Ni silicide phases and morphology in Ni fully silicided gates was investigated for varying deposited Ni to Si thickness ratios and rapid thermal processing…”
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