Search Results - "Upadhyaya, Parag"

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS by Jun-Chau Chien, Upadhyaya, Parag, Jung, Howard, Chen, Stanley, Fang, Wayne, Niknejad, Ali M., Savoj, Jafar, Ken Chang

“…High-speed transceivers embedded inside FPGAs require software-programmable clocking circuits to cover a wide range of data rates across different channels…”
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A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET by Frans, Yohan, Jaewook Shin, Lei Zhou, Upadhyaya, Parag, Jay Im, Kireev, Vassili, Elzeftawi, Mohamed, Hedayati, Hiva, Toan Pham, Asuncion, Santiago, Borrelli, Chris, Zhang, Geoff, Hongtao Zhang, Ken Chang

“…A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at…”
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A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET by Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel Zhaoyin, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan

“…This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver…”
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A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET by Im, Jay, Freitas, Dave, Roldan, Arianne Bantug, Casey, Ronan, Chen, Stanley, Chou, Chuen-Huei Adam, Cronin, Tim, Geary, Kevin, McLeod, Scott, Lei Zhou, Zhuang, Ian, Jaeduk Han, Sen Lin, Upadhyaya, Parag, Zhang, Geoff, Frans, Yohan, Ken Chang

“…A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in…”
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A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET by Frans, Yohan, McLeod, Scott, Hedayati, Hiva, Elzeftawi, Mohamed, Jin Namkoong, Lin, Winson, Jay Im, Upadhyaya, Parag, Ken Chang

“…A 3-tap 64 Gb/s NRZ transmitter using a quad-rate architecture is designed in 16 nm FinFET. The design incorporates circuit techniques and topologies that take…”
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A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET by Upadhyaya, Parag, Poon, Chi Fung, Lim, Siok Wei, Cho, Junho, Roldan, Arianne, Zhang, Wenfeng, Namkoong, Jin, Pham, Toan, Xu, Bruce, Lin, Winson, Zhang, Hongtao, Narang, Nakul, Tan, Kee Hian, Zhang, Geoff, Frans, Yohan, Chang, Ken

“…The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is…”
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A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs by Turker, Didem, Bekele, Ade, Upadhyaya, Parag, Verbruggen, Bob, Ying Cao, Shaojun Ma, Erdmann, Christophe, Farley, Brendan, Frans, Yohan, Ken Chang

“…Direct-RF data converters [1,2] have seen increased adoption in remote-radio-head TX and RX, due to their unparalleled bandwidth and flexibility. However,…”
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A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS by Kok Lim Chan, Kee Hian Tan, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Siok Wei Lim, Roldan, Arianne, Narang, Nakul, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang

“…This paper describes a 32.75-Gb/s voltage-mode transmitter (TX) with three-tap feed forward equalization that is fabricated in a 16-nm FinFET CMOS technology…”
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A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET by Erett, Marc, Hudner, James, Carey, Declan, Casey, Ronan, Geary, Kevin, Hearne, Kay, Neto, Pedro, Mallard, Thomas, Sooden, Vikas, Smyth, Mark, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Wenfeng Zhang, Winson Lin, Xu, Bruce, Chang, Ken

“…This paper presents a flexible-reach 0.5-16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm…”
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A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET by Upadhyaya, Parag, Chi Fung Poon, Siok Wei Lim, Junho Cho, Roldan, Arianne, Wenfeng Zhang, Jin Namkoong, Toan Pham, Xu, Bruce, Lin, Winson, Hongtao Zhang, Narang, Nakul, Kee Hian Tan, Zhang, Geoff, Frans, Yohan, Chang, Ken

“…Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without…”
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A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies by Raj, Mayank, Xie, Chuan, Bekele, Ade, Chou, Adam, Zhang, Wenfeng, Cao, Ying, Kim, Jae Wook, Narang, Nakul, Zhao, Hongyuan, Wang, Yipeng, Tan, Kee Hian, Lin, Winson, Im, Jay, Mahashin, David, Asuncion, Santiago, Upadhyaya, Parag, Frans, Yohan

“…Emerging applications such as machine learning, high-performance computing, and cloud storage continue to push compute demands at the data center. To keep up,…”
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A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS by Frans, Yohan, Carey, Declan, Erett, Marc, Amir-Aslanzadeh, Hesam, Fang, Wayne Y., Turker, Didem, Jose, Anup P., Bekele, Adebabay, Im, Jay, Upadhyaya, Parag, Wu, Zhaoyin Daniel, Hsieh, Kenny C. H., Savoj, Jafar, Chang, Ken

“…This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and…”
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Design Techniques for Load-Independent Direct Bulk-Coupled Low Power QVCO by Peng Liu, Sah, Suman P., Xinmin Yu, Jaeyoung Jung, Upadhyaya, Parag, Nguyen, Tai N., Deukhyoun Heo

“…Design techniques for a load-independent low-power low-phase-noise CMOS LC direct bulk-coupled quadrature voltage-controlled oscillator (DBC-QVCO) is presented…”
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A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs by Savoj, Jafar, Hsieh, Kenny Cheng-Hsiang, Fu-Tai An, Gong, Jason, Jay Im, Xuewen Jiang, Jose, Anup P., Kireev, Vassili, Siok-Wei Lim, Roldan, Arianne, Turker, Didem Z., Upadhyaya, Parag, Wu, Daniel, Ken Chang

“…This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques…”
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Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET by Turker, Didem, Upadhyaya, Parag, Im, Jay, Stanley Chen, Frans, Yohan, Ken Chang

“…This paper describes circuit techniques for high speed transceivers used in FPGA applications. Three architectures in 16nm FinFET encompassing NRZ and PAM4…”
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Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS by Savoj, Jafar, Aslanzadeh, Hesam, Carey, Declan, Erett, Marc, Fang, Wayne, Frans, Yohan, Hsieh, Kenny, Im, Jay, Jose, Anup, Turker, Didem, Upadhyaya, Parag, Wu, Daniel, Chang, Ken

“…This paper describes the design techniques to achieve wideband flexible-reach operation in a fully-adaptive transceiver embedded in a 20nm CMOS FPGA. The…”
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3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET by Frans, Yohan, McLeod, Scott, Hedayati, Hiva, Elzeftawi, Mohamed, Jin Namkoong, Lin, Winson, Im, Jay, Upadhyaya, Parag, Ken Chang

“…Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers is projected to double…”
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High Performance PIN Diode in 0.18-μm SiGe BiCMOS Process for Broadband Monolithic Control Circuits by Pinping Sun, Parag Upadhyaya, Le Wang, Dong-Ho Jeong, Deukhyoun Heo

“…This paper presents a novel high isolation and low insertion loss broadband PIN diode implemented in a standard 0.18 μm SiGe BiCMOS process for upper X-band…”
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A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET by Erett, Marc, Hudner, James, Carey, Declan, Casey, Ronan, Geary, Kevin, Hearne, Kay, Neto, Pedro, Mallard, Thomas, Sooden, Vikas, Smyth, Mark, Frans, Yohan, Im, Jay, Upadhyaya, Parag, Wenfeng Zhang, Winson Lin, Xu, Bruce, Chang, Ken

“…This paper presents a flexible 0.5-16.3Gb/s serial transceiver - fabricated in 16nm FinFET CMOS - and consuming 219mW/channel at 16.3Gb/s. The transceiver is…”
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6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET by Im, Jay, Freitas, Dave, Roldan, Arianne, Casey, Ronan, Chen, Stanley, Chou, Adam, Cronin, Tim, Geary, Kevin, McLeod, Scott, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Upadhyaya, Parag, Zhang, Geoff, Frans, Yohan, Ken Chang

“…The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up…”
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