Search Results - "Un-Ku Moon"

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  1. 1

    A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter by Xu, Yang, Hu, Hang, Muhlestein, Jason, Moon, Un-Ku

    Published in IEEE journal of solid-state circuits (01-10-2020)
    “…A compact coupled source followers (CSFs)-based low-pass filter (LPF) topology is presented with excellent power efficiency and high linearity. It synthesizes…”
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    Journal Article
  2. 2

    A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier by ElShater, Ahmed, Venkatachala, Praveen Kumar, Lee, Calvin Yoji, Muhlestein, Jason, Leuenberger, Spencer, Sobue, Kazuki, Hamashita, Koichi, Moon, Un-Ku

    Published in IEEE journal of solid-state circuits (01-12-2019)
    “…Low-noise ring amplifiers required for high-precision analog-digital converters (ADCs) greater than 16 b remain unexplored. This article demonstrates a…”
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    Journal Article
  3. 3

    Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells by Weaver, Skyler, Hershberg, Benjamin, Un-Ku Moon

    “…It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog…”
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    Journal Article
  4. 4

    A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting by Li, Manxin, Lee, Calvin Yoji, Venkatachala, Praveen Kumar, ElShater, Ahmed, Miyahara, Yuichi, Sobue, Kazuki, Tomioka, Koji, Moon, Un-Ku

    Published in IEEE journal of solid-state circuits (01-12-2023)
    “…Input buffers can be used to reduce the input load of high-resolution discrete-time (DT) Nyquist analog-to-digital converters (ADCs), which can be challenging…”
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    Journal Article
  5. 5

    An Oversampling Stochastic ADC Using VCO-Based Quantizers by Sun, Hyuk, Sobue, Kazuki, Hamashita, Koichi, Moon, Un-Ku

    “…An oversampling stochastic analog-to-digital converter is presented. This stochastic converter spatially averages quantization errors in multiple…”
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    Journal Article
  6. 6

    Ring Amplifiers for Switched Capacitor Circuits by Hershberg, B., Weaver, S., Sobue, K., Takeuchi, S., Hamashita, K., Un-Ku Moon

    Published in IEEE journal of solid-state circuits (01-12-2012)
    “…In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments,…”
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    Journal Article Conference Proceeding
  7. 7

    Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR by Shi, Lukang, Thiagarajan, Eashwar, Singh, Rajiv, Hancioglu, Erhan, Moon, Un-Ku, Temes, Gabor C.

    “…A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator,…”
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    Journal Article
  8. 8

    A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators by Lee, Calvin Yoji, Venkatachala, Praveen Kumar, ElShater, Ahmed, Moon, Un-Ku

    “…This brief presents a high-resolution ADC which makes use of the pseudo-pseudo-differential noise filtering technique in an oversampling ADC architecture with…”
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    Journal Article
  9. 9

    An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain by Gregoire, B.R., Un-Ku Moon

    Published in IEEE journal of solid-state circuits (01-12-2008)
    “…Correlated level shifting (CLS) is introduced as a new switched-capacitor technique to provide true rail-to-rail performance while reducing errors from finite…”
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    Journal Article Conference Proceeding
  10. 10

    A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator by Sun, Hyuk, Sobue, Kazuki, Hamashita, Koichi, Anand, Tejasvi, Moon, Un-Ku

    Published in IEEE journal of solid-state circuits (01-02-2020)
    “…A spread-spectrum clock generator is proposed based on an in-band phase modulation. In a charge-pump phase-locked loop configuration, the input phase…”
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    Journal Article
  11. 11

    A Digital PLL With a Stochastic Time-to-Digital Converter by Kratyuk, V., Hanumolu, P.K., Ok, K., Un-Ku Moon, Mayaram, K.

    “…A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency…”
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    Journal Article
  12. 12

    A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique by Xu, Yang, Venkatachala, Praveen Kumar, Hu, Yue, Leuenberger, Spencer, Temes, Gabor C., Moon, Un-Ku

    “…A highly reconfigurable charge-domain switched-gm-C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge-sharing technique…”
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    Journal Article
  13. 13

    Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs by Waters, Allen, Muhlestein, Jason, Un-Ku Moon

    “…A practical model for characterizing comparator metastability errors in SAR ADCs is presented, and is used to analyze not only the conventional SAR but also…”
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    Journal Article
  14. 14

    Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits by He, Tao, Kareppagoudr, Manjunath, Zhang, Yi, Caceres, Emanuel, Moon, Un-Ku, Temes, Gabor C.

    “…The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the…”
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    Journal Article
  15. 15

    74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain by Maghari, N., Sunwoo Kwon, Un-Ku Moon

    Published in IEEE journal of solid-state circuits (01-08-2009)
    “…This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop…”
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    Journal Article
  16. 16

    Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp by Hershberg, B, Weaver, S, Un-Ku Moon

    Published in IEEE journal of solid-state circuits (01-12-2010)
    “…Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution…”
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    Journal Article Conference Proceeding
  17. 17

    A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer by Taehwan Oh, Maghari, N., Un-Ku Moon

    Published in IEEE journal of solid-state circuits (01-06-2013)
    “…In this paper, a new second-order discrete-time ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. The first quantization step (coarse)…”
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    Journal Article
  18. 18

    PLL-SAR: A New High-Speed Analog to Digital Converter Architecture by Vesely, Vladimir, Lee, Calvin Yoji, Anand, Tejasvi, Moon, Un-Ku

    “…A novel, high bandwidth Phase-Locked-Loop Successive Approximation Register (PLL-SAR) ADC topology is proposed. To ensure fast loop settling without power…”
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    Conference Proceeding
  19. 19

    A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC by Li, Manxin, Lee, Calvin Yoji, Wang, Hanyu, Temes, Gabor C., Moon, Un-Ku

    “…Pseudo-Pseudo-Differential (PPD) architecture can achieve higher power-efficiency with greatly reduced hardware complexity compared with fully- or…”
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    Conference Proceeding
  20. 20

    A chopper-stabilized source follower coupling based low-pass filter with noise reduction by Xu, Yang, Moon, Un-Ku

    “…A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single…”
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    Journal Article