Search Results - "Umimoto, H."
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1
Three-dimensional numerical simulation of local oxidation of silicon
Published in IEEE transactions on electron devices (01-03-1991)“…The nitride mask bending stress is modeled in three dimensions by using the beam bending theory. The stress effect on the oxide growth is taken into account…”
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2
The inverse-narrow-width effect of LOCOS isolated n-MOSFET in a high-concentration p-well
Published in IEEE electron device letters (01-12-1992)“…The inverse-narrow-width effect (INWE) of a LOCOS-isolated n-MOSFET formed in high concentration p-wells is described. The threshold behavior is characterized…”
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3
Numerical simulation of stress-dependent oxide growth at convex and concave corners of trench structures
Published in IEEE electron device letters (01-07-1989)“…A numerical simulation of oxide thinning at convex and concave corners of trench structures is discussed. The stress effect on the oxide growth is modeled by…”
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4
SMART-II: a three-dimensional CAD model for submicrometer MOSFET's
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-05-1991)“…The authors describe a three-dimensional CAD model for submicrometer MOSFETs. The model has been implemented in a three-dimensional process/device integrated…”
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5
SMART-P: rigorous three-dimensional process simulator on a supercomputer
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-06-1988)“…A description is given of a three-dimensional process simulator, named SMART-P, that is based on the finite-difference approach to the supercomputer FACOM…”
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6
Numerical modeling of nonplanar oxidation coupled with stress effects
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-06-1989)“…The study focuses on the numerical solution method based on a finite-difference approach with the coordinate transformation method for simulating the nonplanar…”
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7
A self-aligned retrograde twin-well structure with buried p+-layer
Published in IEEE electron device letters (01-06-1989)“…The retrograde twin wells and buried p( ) layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is…”
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8
Analysis of As, P Diffusion and Defect Evolution during Sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach
Published in 2007 IEEE International Electron Devices Meeting (01-01-2007)“…n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling…”
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9
Improvement of RSF for a statistical design of lithographic process
Published in 1997 2nd International Workshop on Statistical Metrology (1997)“…A statistical design method for lithographic process using the RSM (Response Surface Method) is developed. The RSF for CD (Critical Dimension) in optical…”
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10
Non-destructive inverse modeling of copper interconnect structure for 90nm technology node
Published in International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003 (2003)“…We propose non-destructive inverse modeling of copper interconnect cross-sectional structures, which reproduces the pitch dependence of intraand interlayer…”
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11
A self-aligned retrograde twin-well structure with buried p/sup +/-layer
Published in IEEE transactions on electron devices (01-07-1990)“…A self-aligned retrograde twin-well structure with a buried p/sup +/-layer surrounding the n-well is presented. The retrograde twin well and buried p/sup…”
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12
A self-aligned retrograde twin-well structure with buried p/sup +/-layer
Published in IEEE electron device letters (01-06-1989)“…The retrograde twin wells and buried p/sup +/ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is…”
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Journal Article -
13
A self-aligned retrograde twin-well structure with buried p+-layer
Published in IEEE transactions on electron devices (01-07-1990)“…A self-aligned retrograde twin-well structure with a buried p( )-layer surrounding the n-well is presented. The retrograde twin well and buried p( )-layer are…”
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14
A self-aligned retrograde twin-well structure with buried p super(+)-layer
Published in IEEE electron device letters (01-01-1989)“…This paper reports a self-aligned retrograde twin-well structure with a buried p super(+)-layer surrounding the n-well. The retrograde twin wells and buried p…”
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15
A Three-Dimensional Dynamic Simulation of Borophosphosilicate Glass Flow
Published in 1991 Symposium on VLSI Technology (1991)“…This paper describes a three-dimensional simulation of Borophosphosilicate glass (BPSG) flow for the first time. The viscosity of BPSG is modeled by…”
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16
Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices
Published in 1995 Symposium on VLSI Technology. Digest of Technical Papers (1995)“…The effect of the gate to drain capacitance on low voltage operated CMOS devices is investigated. It is found that the Miller and feed-forward effects are…”
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17
A 0.18 /spl mu/m Ti-salicided p-MOSFET with shallow junctions fabricated by rapid thermal processing in an NH/sub 3/ ambient
Published in International Electron Devices Meeting. Technical Digest (1996)“…This paper reports a 0.18 /spl mu/m Ti-salicided p-MOSFET with shallow junctions fabricated by rapid thermal processing (RTP) in an NH/sub 3/ ambient and low…”
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18
High speed 0.1 /spl mu/m dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide
Published in International Electron Devices Meeting. Technical Digest (1996)“…A novel dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide is proposed. This technology suppresses boron penetration for pMOS,…”
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19
A statistical critical dimension control at CMOS cell level
Published in International Electron Devices Meeting. Technical Digest (1996)“…This paper reports a new statistical methodology for controlling the spreads of the CD (critical dimension) distribution in the lithography process. Response…”
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20
Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow-Width Effect of n-MOS Threshold Voltages
Published in 1985 Symposium on VLSI Technology. Digest of Technical Papers (01-05-1985)“…Trench isolation technology with boron implanted vertical side-walls is presented andproved to be useful for completely suppressing humps in subthreshold…”
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