Search Results - "Uchibori, Chihiro. J."

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure by Mizushima, Yoriko, Kitada, Hideki, Uchibori, Chihiro J, Maeda, Nobuhide, Kodama, Shoichi, Kim, Youngsuk, Fujimoto, Koji, Yoshimi, Seiichi, Nakamura, Tomoji, Ohba, Takayuki

“…Crack formation due to thermomechanical stresses generated by a dielectric polymer thicker than 20 μm and by that with high modulus during the bumpless…”
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Formation of WSi-based ohmic contacts to n-type GaAs by Oku, Takeo, Furumai, Masaki, Uchibori, Chihiro J., Murakami, Masanori

“…An outcome of the indirect doping concept conceived recently in NiGe-based Ohmic contacts has led to the development of annealed WSi-based Ohmic contacts to…”
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SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET by Uemura, T, Tosaka, Y, Matsuyama, H, Shono, K, Uchibori, C J, Takahisa, K, Fukuda, M, Hatanaka, K

“…We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event…”
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Solder crack simulation using SPH particle method with submodeling technique by Uchibori, Chihiro J., Sakuyama, Seiki, Sakai, Yuzuru, Thyon Su-I, Watanabe, Takayuki, Yamagata, Nobuki

“…In order to improve the mechanical reliability of IC packages crack generation and its propagation which are caused by such as Chip Package Interaction (CPI)…”
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Structural effects on Chip Package Interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip-chip package by Lee, Michael G, Uchibori, Chihiro J

“…The effects of structural design on the mechanical reliability of Cu/low-k multi-layer interconnects are investigated using finite element method. The Chip…”
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InxGa1-xAs ohmic contacts to n-type GaAs with a tungsten nitride barrier by UCHIBORI, C. J, OHTANI, Y, OKU, T, ONO, N, MURAKAMI, M

“…Significant reduction of the contact resistance of In0.7Ga0.3As/Ni/W contacts (which were previously developed by sputtering in our laboratory) was achieved by…”
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Chip Package Interaction analysis for Cu/Ultra low-k large die Flip Chip Ball Grid Array by Uchibori, C.J., Lee, M., Xeufeng Zhang, Ho, P.S.

“…The impact of Chip-Package Interaction (CPI) which is caused by the mismatch in the coefficient of thermal expansion (CTE) between substrate and chip in a Flip…”
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Formation mechanism of InxGa1−xAs ohmic contacts to n-type GaAs prepared by radio frequency sputtering by Uchibori, Chihiro J., Okunishi, Masayuki, Oku, T., Otsuki, A., Ono, Naoki, Murakami, Masanori

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InxGa1-xAs ohmic contacts to n-type GaAs prepared by sputter deposition by OKUNISHI, M, UCHIBORI, C. J, OKU, T, OTSUKI, A, ONO, N, MURAKAMI, M

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In situ x-ray photoelectron spectroscopy measurement during Ta deposition on low- k dielectric SiLK by Uchibori, Chihiro. J., Kimura, Takahiro

“…The bonding energy of Ta and C was measured by in situ x-ray photoelectron spectroscopy during sequential tantalum (Ta) deposition on low- k SiLK™. A tantalum…”
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Direct Attach of Photonic Components on Substrates With Optical Interconnects by Glebov, A.L., Uchibori, C.J., Lee, M.G.

“…Direct attach of lasers and photodiodes on boards with optical interconnects can facilitate high-density packaging of high-speed optical components. For the…”
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Thermal stress analysis of FCBGA during cooling under reflow process by Uchibori, C J, Lee, M

“…Thermal stresses in Flip Chip Ball Grid Array (FCBGA) generated by the Chip Package Interaction (CPI) while cooling during the reflow process were calculated…”
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Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die by Uchibori, C.J., Lee, M.

“…Die size effects on chip package interaction for Cu/ultra low-k interconnect in flip chip package were investigated using mechanical and thermal analysis. The…”
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Investigation of Interconnect Design on Chip Package Interaction and Mechanical Reliability of Cu/Low-k Multi-Layer Interconnects in Flip Chip Package by Uchibori, Chihiro J., Zhang, Xuefeng, Ho, Paul S., Nakamura, Tomoji

“…Impacts of the interconnect design on the mechanical reliability of Cu/low-k multi-layer interconnects were investigated using Finite Element Analysis. The…”
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Chip Package Interaction and mechanical reliability impact on Cu/ultra low-k interconnects in Flip Chip package by Uchibori, C.J., Xuefeng Zhang, Ho, P.S., Nakamura, T.

“…The chip package interaction (CPI) induced by the mismatch in coefficient of thermal expansion (CTE) between chip and package in a flip chip ball grid array…”
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Effects of Chip-Package Interaction on Mechanical Reliability of Cu Interconnects for 65nm Technology Node and Beyond by Uchibori, C.J., Xuefeng Zhang, Ho, P.S., Nakamura, T.

“…The impact of chip-package interaction (CPI) on the mechanical reliability of Cu low-k interconnects was investigated using a 3D multi-level sub-modeling…”
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Impact of chip-package interaction on reliability of Cu/ultra low-k interconnects for 65nm technology and beyond by Uchibori, C.J., Xuefeng Zhang, Ho, P.S., Nakamura, T.

“…The die attach process to flip chip package using Pb-free solder can impact the mechanical reliability of Cu/ultra low-k interconnects for 65nm technology and…”
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Investigation of Mechanical Reliability of Cu/low-k Multi-layer Interconnects in Flip Chip Packages by Uchibori, C.J., Xuefeng Zhang, Sehyuk Im, Ho, P.S., Nakamura, T.

“…The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated…”
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