Search Results - "Tutanescu, I."

On a FPGA implementation of BCH codes by Ionescu, L, Anton, C, Tutănescu, I, Mazăre, A, Şerban, G

“…Our paper presents the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) encoder and decoder using a Field Programmable Gate Array (FPGA) reconfigurable…”
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Error correction and detection system based on Hopfield networks by Ionescu, L., Anton, C., Tutanescu, I., Mazare, A., Serban, G.

“…Error correction is a basic feature of a communication system. Therefore there are sought, and still seek, many solutions to this problem. In this paper we…”
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Hybrid error detecting and correcting system using hardware associative memories by Tutanescu, I., Anton, C., Ionescu, L., Serban, G., Mazare, A.

“…This paper presents a solution of design and implementation of a hardware error correction and detection system using associative memories. This type of memory…”
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Using associative memories in coding theory for communication channels by Anton, C., Ionescu, L., Tutanescu, I., Mazare, A., Serban, G.

“…Our paper presents a solution for designing and implementation of a hardware error correction and detection circuit using associative memories. Associative…”
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Elliptic Curves Cryptosystems approaches by Tutanescu, I., Anton, C., Ionescu, L., Caragata, D.

“…This paper take in discussion an important area of security: Elliptic Curves Cryptosystems (ECC) are the next frontier in the use of security mechanisms by…”
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Reed-Muller decoder with associative memories by Ionescu, L., Anton, C., Tutanescu, I., Mazare, A., Serban, G.

“…In this paper we present a solution for designing a Reed-Muller decoder using associative memories based on Hopfield networks. The decoding with classical…”
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An error detection and correction system based on associative memories by Anton, C., Ionescu, L., Tutanescu, I., Mazare, A., Serban, G., Oprea, A.

“…Associative memories have the property to allow the searching of a binary stored value, having as an input data a partial amount of this value. This property…”
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Implementation of a 64-bit hybrid SR-ARQ algorithm on FPGA by Serban, G., Anton, C., Ionescu, L., Tutanescu, I., Mazare, A.

“…Forward error correction (FEC) and automatic request (ARQ) are common techniques used to treat transmission errors when data are transmitted over noisy…”
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Secure TCP/IP communications over DVB-S/DVB-RCS using chaotic sequences by Caragata, D., El Assad, S., Tutanescu, I., Sofron, E.

“…The DVB-S (Digital Video Broadcasting - Satellite) was originally developed as a TV broadcasting protocol. Later on two encapsulation protocols were developed…”
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Secure IP multicast over satellite by Caragata, D, Sofron, E, Tutanescu, I, Assad, S E

“…We notice a very strong "all IP" trend characterizing today's communication technology. There is a powerful IP backbone in place, but, in some cases, the "last…”
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Detecting errors in digital communications with CRC codes implemented with FPGA by Anton, C., Ionescu, L., Tutanescu, I., Mazare, A., Serban, G.

“…Generally speaking, cyclic redundancy checks (CRCs) are used to detect errors from noise in digital data transmission. The technique is also sometimes applied…”
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H-ARQ system for real time error detection and correction based on hardware associative memories by Serban, G., Anton, C., Ionescu, L. M., Tutanescu, I., Mazare, A.

“…This paper presents a solution of design and implementation of a hardware error correction and detection circuit using associative memories. This type of…”
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FPGA-implemented CRC algorithm by Anton, C., Ionescu, L., Tutanescu, I., Mazare, A., Serban, G.

“…Generally speaking, cyclic redundancy checks (CRCs) are used to detect errors from noise in digital data transmission. The technique is also sometimes applied…”
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