Search Results - "Tummala, R.R."

Gigabit wireless: system-on-a-package technology by TUMMALA, R.R., LASKAR, J.

“…The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost,…”
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SOP: what is it and why? A new microsystem-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade by Tummala, R.R.

“…In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and…”
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Colloidal processing of polymer ceramic nanocomposite integral capacitors by Windlass, H., Raj, P.M., Balaraman, D., Bhattacharya, S.K., Tummala, R.R.

“…Polymer ceramic composites form a suitable material system for low temperature fabrication of embedded capacitors appropriate for the MCM-L technology…”
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Hybrid Integration of End-to-End Optical Interconnects on Printed Circuit Boards by Zhaoran Rena Huang, Guidotti, D., Lixi Wan, Yin-Jung Chang, Jianjun Yu, Jin Liu, Hung-Fei Kuo, Gee-Kung Chang, Fuhan Liu, Tummala, R.R.

“…This paper discusses the integration of an end-to-end optical interconnect testbed on printed circuit boards using inexpensive off-the-shelf, bare die,…”
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Thermomechanical Reliability of Nickel Pillar Interconnections Replacing Flip-Chip Solder Without Underfill by Aggarwal, A.O., Raj, P.M., Baik-Woo Lee, Myung Jin Yim, Iyer, M., Wong, C.P., Tummala, R.R.

“…Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections…”
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Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates by Lee, K.J., Damani, M., Pucha, R.V., Bhattacharya, S.K., Tummala, R.R., Sitaraman, S.K.

“…Understanding and quantifying the RLC characteristics of the embedded passives under thermomechanical deformation during fabrication and accelerated thermal…”
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Lead-Free Solder Films Via Novel Solution Synthesis Routes by Aggarwal, A.O., Abothu, I.R., Raj, P.M., Sacks, M.D., Tummala, R.R.

“…We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solders. Novel processes with these routes were developed and…”
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Integral passives for next generation of electronic packaging: application of epoxy/ceramic nanocomposites as integral capacitors by Bhattacharya, S.K, Tummala, R.R

“…The consumer demand for product miniaturization with increased functionality and reliability is ever growing in the electronic industry. Integral passive is a…”
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Reliability assessment of microvias in HDI printed circuit boards by Fuhan Liu, Jicun Lu, Sundaram, V., Sutter, D., White, G., Baldwin, D.F., Tummala, R.R.

“…Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density…”
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Foreword Special Issue on System-On-Package (SOP) by Tummala, R.R.

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The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade by Tummala, R.R., Swaminathan, M., Tentzeris, M.M., Laskar, J., Gee-Kung Chang, Sitaraman, S., Keezer, D., Guidotti, D., Zhaoran Huang, Kyutae Lim, Lixi Wan, Bhattacharya, S.K., Sundaram, V., Fuhan Liu, Raj, P.M.

“…From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to…”
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Meniscus coating: a low-cost polymer deposition method for system-on-package (SOP) substrates by Bhattacharya, S.K., Moon, K.S., Tummala, R.R., May, G.S.

“…Meniscus coating is a low-cost deposition method that can be used to apply polymers in solution as thin films to the surface of electronics packaging…”
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Polymer-ceramic nanocomposite capacitors for system-on-package (SOP) applications by Windlass, H., Markondeya Raj, P., Balaraman, D., Bhattacharya, S.K., Tummala, R.R.

“…This work focuses on optimizing the dispersion of nanosized ceramic particles for achieving higher dielectric constant, thereby higher capacitance density in…”
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Development of high performance interfill materials for system chips technology by Jiali Wu, Bhattacharya, S., Lloyd, C., Wong, C.P., Pogge, H.B., Tummala, R.R.

“…An innovative precisely interconnected chip (PIC) technology is currently under development at IBM to seek more effective means of creating system chips. The…”
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New 3-D Chip Stacking Architectures by Wire-On-Bump and Bump-On-Flex by Baik-Woo Lee, Jui-Yun Tsai, Hotae Jin, Yoon, C.K., Tummala, R.R.

“…Two new 3-D chip stacking technologies, wire-on-bump (WOB) and bump-on-flex (BOF), are proposed and demonstrated with their prototypes. The WOB and BOF…”
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An automated workcell for meniscus coating on 24-in packaging substrates by Bhattacharya, S.K., Bhatevara, S., Sutter, D.A., Kamen, E.W., May, G.S., Tummala, R.R.

“…Improved coating procedures are essential to the success of low-cost large substrate multichip module (MCM) fabrication, as existing coaters are slow and waste…”
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Metal-Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging by Aggarwal, A.O., Raj, P.M., Tummala, R.R.

“…The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its…”
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Next-generation microvia and global wiring technologies for SOP by Sundaram, V., Tummala, R.R., Fuhan Liu, Kohl, P.A., Jun Li, Bidstrup-Allen, S.A., Fukuoka, Y.

“…As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels…”
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Chip-to-chip optoelectronics SOP on organic boards or packages by Gee-Kung Chang, Guidotti, D., Fuhan Liu, Yin-Jung Chang, Zhaoran Huang, Sundaram, V., Balaraman, D., Hegde, S., Tummala, R.R.

“…In this paper, we demonstrate compatibility of hybrid, large-scale integration of both active and passive devices and components onto standard printed wiring…”
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Development of Stretch Solder Interconnections for Wafer Level Packaging by Rajoo, R., Lim, S.S., Wong, E.H., Hnin, W.Y., Seah, S.K.W., Tay, A.A.O., Iyer, M., Tummala, R.R.

“…A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable…”
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