Search Results - "Tullsen, Dean M."

Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management by Taram, Mohammadkazem, Venkat, Ashish, Tullsen, Dean M.

“…Modern instruction set decoders feature translation of native instructions into internal micro-ops to simplify the CPU design and improve instruction-level…”
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Redefining the Role of the CPU in the Era of CPU-GPU Integration by Arora, Manish, Nath, Siddhartha, Mazumdar, Subhra, Baden, Scott B., Tullsen, Dean M.

“…We've seen the quick adoption of GPUs as general-purpose computing engines in recent years, fueled by high computational throughput and energy efficiency…”
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I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches by Ren, Xida, Moody, Logan, Taram, Mohammadkazem, Jordan, Matthew, Tullsen, Dean M., Venkat, Ashish

“…Modern Intel, AMD, and ARM processors translate complex instructions into simpler internal micro-ops that are then cached in a dedicated on-chip structure…”
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Heterogeneous chip multiprocessors by Kumar, R., Tullsen, D.M., Jouppi, N.P., Ranganathan, P.

“…Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating…”
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MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories by Prodromou, Andreas, Meswani, Mitesh, Jayasena, Nuwan, Loh, Gabriel, Tullsen, Dean M.

“…In the near future, die-stacked DRAM will be increasingly present in conjunction with off-chip memories in hybrid memory systems. Research on this subject…”
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The case for colocation of high performance computing workloads by Breslow, Alex D., Porter, Leo, Tiwari, Ananta, Laurenzano, Michael, Carrington, Laura, Tullsen, Dean M., Snavely, Allan E.

“…Summary The current state of practice in supercomputer resource allocation places jobs from different users on disjoint nodes both in terms of time and space…”
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Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems by Arora, Manish, Manne, Srilatha, Paul, Indrani, Jayasena, Nuwan, Tullsen, Dean M.

“…Overall energy consumption In modern computing systems Is significantly Impacted by Idle power. Power gating, also known as C6, Is an effective mechanism to…”
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Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance by Kumar, Rakesh, Tullsen, Dean M., Ranganathan, Parthasarathy, Jouppi, Norman P., Farkas, Keith I.

“…A single-ISA heterogeneous multi-core architecture is achip multiprocessor composed of cores of varying size, performance,and complexity. This paper…”
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Underclocked Software Prefetching: More Cores, Less Energy by Kamruzzaman, Md, Swanson, Steven, Tullsen, Dean M.

“…Power consumption is a concern for helper-thread prefetching that uses extra cores to speed up the single-thread execution, because power consumption increases…”
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Eliminating Redundant Computation and Exposing Parallelism through Data-Triggered Threads by Hung-Wei Tseng, Tullsen, D. M.

“…Unlike threads in parallel programs created by conventional programming, data-triggered threads are initiated when a memory value is changed. By expressing…”
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Handling long-latency loads in a simultaneous multithreading processor by Tullsen, D.M., Brown, J.A.

“…Simultaneous multithreading architectures have been defined previously with fully shared execution resources. When one thread in such an architecture…”
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Resistive Computation: A Critique by Mahmoodi, Hamid, Lakshmipuram, Sridevi Srinivasan, Arora, Manish, Asgarieh, Yashar, Homayoun, Houman, Lin, Bill, Tullsen, Dean M.

“…Resistive Computation was suggested by [6] as an idea for tacking the power wall by replacing conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based…”
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Dynamic speculative precomputation by Collins, J.D., Tullsen, D.M., Wang, Hong, Shen, J.P.

“…A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based…”
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Editorial: Special Section on CMP Architectures by Iyer, Ravi, Tullsen, Dean M.

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Inter-socket victim cacheing for platform power reduction by Mazumdar, Subhra, Tullsen, Dean M, Song, Justin

“…On a multi-socket architecture with load below peak, as is often the case in a server installation, it is common to consolidate load onto fewer sockets to save…”
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A Tree Based Router Search Engine Architecture with Single Port Memories by Baboescu, Florin, Tullsen, Dean M., Rosu, Grigore, Singh, Sumeet

“…Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high…”
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An event-driven multithreaded dynamic optimization framework by Weifeng Zhang, Calder, B., Tullsen, D.M.

“…Dynamic optimization has the potential to adapt the program's behavior at run-time to deliver performance improvements over static optimization. Dynamic…”
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Conjoined-Core Chip Multiprocessing by Kumar, Rakesh, Jouppi, Norman P., Tullsen, Dean M.

“…Chip Multiprocessors (CMP) and Simultaneous Multi-threading (SMT) are two approaches that have been proposed to increase processor efficiency. We believe these…”
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Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor by Venkat, Ashish, Tullsen, Dean M.

“…Heterogeneous multicore architectures have the potential for high performance and energy efficiency. These architectures may be composed of small…”
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Simultaneous multithreading: maximizing on-chip parallelism by Tullsen, Dean M., Eggers, Susan J., Levy, Henry M.

“…This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple…”
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