Search Results - "Tsertov, Anton"

Software-based self-test generation for microprocessors with high-level decision diagrams by Jasnetski, Artjom, Ubar, Raimund, Tsertov, Anton, Brik, Marina

“…This article presents a novel approach to automated behavioural level test program generation for microprocessors, using the model of high-level decision…”
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Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL by Damljanovic, Aleksa, Jutman, Artur, Portolan, Michele, Sanchez, Ernesto, Squillero, Giovanni, Tsertov, Anton

“…A fundamental part of the new IEEE Std 1687 is the Instrument Connectivity Language (ICL), which allows for abstract description of the scan network. The big…”
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A suite of IEEE 1687 benchmark networks by Tsertov, Anton, Jutman, Artur, Devadze, Sergei, Reorda, Matteo Sonza, Larsson, Erik, Zadegan, Farrokh Ghani, Cantoro, Riccardo, Montazeri, Mehrdad, Krenz-Baath, Rene

“…The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set…”
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Software-based self-test generation for microprocessors with high-level decision diagrams/Korgtasemega otsustusdiagrammidel pohinev testprogrammide suntees mikroprotsessoritele by Jasnetski, Artjom, Ubar, Raimund, Tsertov, Anton, Brik, Marina

“…This paper presents a novel approach to automated behavioural level test program generation for microprocessors using the model of high-level decision diagrams…”
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On-Chip Sensors Data Collection and Analysis for SoC Health Management by Shibin, Konstantin, Jenihhin, Maksim, Jutman, Artur, Devadze, Sergei, Tsertov, Anton

“…Data produced by on-chip sensors in modern SoCs contains a large amount of information such as occurring faults, aging status, accumulated radiation dose,…”
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On-Chip Sensors Data Collection and Analysis for SoC Health Management by Shibin, Konstantin, Jenihhin, Maksim, Jutman, Artur, Devadze, Sergei, Tsertov, Anton

“…Data produced by on-chip sensors in modern SoCs contains a large amount of information such as occurring faults, aging status, accumulated radiation dose,…”
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Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs by Selg, Hardi, Shibin, Konstantin, Tsertov, Anton, Jenihhin, Maksim, Ellervee, Peeter, Raik, Jaan

“…This paper proposes a novel in-field ML-assisted fault localization and fault management approach for intermittent faults in RISC-V microprocessor cores…”
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Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks by Damljanovic, Aleksa, Jutman, Artur, Squillero, Giovanni, Tsertov, Anton

“…The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new…”
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Automatic SoC Level Test Path Synthesis Based on Partial Functional Models by Tsertov, A., Ubar, R., Jutman, A., Devadze, S.

“…While system level test was a topic of extremely high interest during the last decades, the cost of the test program development was continuously growing. The…”
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Automated software-based self-test generation for microprocessors by Jasnetski, Artjom, Ubar, Raimund, Tsertov, Anton

“…Software-based self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents a tool for automated Software-Based…”
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IEEE 1687 Compliant Ecosystem for Embedded Instrumentation Access and In-Field Health Monitoring by Tsertov, Anton, Jutman, Artur, Shibin, Konstantin, Devadze, Sergei

“…The ongoing research in the adjoin fields of failure resilience, health monitoring, fault management has also shown a widening interest in IEEE 1687 Std…”
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Keynote: Cost-Efficient Reliability for Edge-AI Chips by Jenihhin, Maksim, Taheri, Mahdi, Cherezova, Natalia, Ahmadilivani, Mohammad Hasan, Selg, Hardi, Jutman, Artur, Shibin, Konstantin, Tsertov, Anton, Devadze, Sergei, Kodamanchili, Rama Mounika, Rafiq, Ahsan, Raik, Jaan, Daneshtalab, Masoud

“…Very recently, Artificial Intelligence started undergoing a remarkable transformation by moving closer to the source of data, thus establishing the Edge AI…”
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On automatic software-based self-test program generation based on high-level decision diagrams by Jasnetski, Artjom, Ubar, Raimund, Tsertov, Anton

“…Software-Based Self-Testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents an approach for automatic SBST program…”
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High-level test data generation for software-based self-test in microprocessors by Oyeniran, Adeboye Stephen, Jasnetski, Artjom, Tsertov, Anton, Ubar, Raimund

“…A new high-level fault model and test generation method for software-based self-test in microprocessors (MP) is proposed and investigated. The model is derived…”
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New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams by Jasnetski, Artjom, Raik, Jaan, Tsertov, Anton, Ubar, Raimund

“…The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general…”
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High-level modeling and testing of multiple control faults in digital systems by Jasnetski, Artjom, Oyeniran, Stephen Adeboye, Tsertov, Anton, Scholzel, Mario, Ubar, Raimund

“…A new method for high level fault modeling to improve the test generation for the control parts of digital systems was proposed. We developed a new high-level…”
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Software-based self-test generation for microprocessors with high-level decision diagrams by Ubar, Raimund, Tsertov, Anton, Jasnetski, Artjom, Brik, Marina

“…Software-based self-testing (SBST) is a well known non-intrusive method for processor testing. Its applications have been intensively studied by the research…”
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Laboratory framework TEAM for investigating the dependability issues of microprocessor systems by Jasnetski, Artjom, Ubar, Raimund, Tsertov, Anton, Kruus, Helena

“…We propose a laboratory research and student training oriented framework consisting of Test Evaluation Automated Means (TEAM) as a set of tools for evaluating…”
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On in-system programming of non-volatile memories by Tsertov, Anton, Devadze, Sergei, Jutman, Artur, Jasnetski, Artjom

“…With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly…”
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SoC and Board Modeling for Processor-Centric Board Testing by Tsertov, A., Ubar, R., Jutman, A., Devadze, S.

“…Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral…”
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