Search Results - "Tseng Hsing-Huang"

Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap by Ji-Woon Yang, Zeitzoff, P.M., Hsing-Huang Tseng

“…The speed performance of a double-gate (DG) FinFET CMOS with gate-source/drain (G-S/D) underlap is investigated using 2-D device and mixed-mode circuit…”
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Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- k/Metal Gate Stack Device Reliability and Performance Enhancement by Tseng Hsing-Huang, Tobin, P.J., Kalpat, S., Schaeffer, J.K., Ramon, M.E., Fonseca, L.R.C., Jiang, Z.X., Hegde, R.I., Triyoso, D.H., Semavedam, S.

“…Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-fc deposition, we show significant device…”
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Si tunnel transistors with a novel silicided source and 46mV/dec swing by Kanghoon Jeon, Wei-Yip Loh, Patel, P, Chang Yong Kang, Jungwoo Oh, Bowonder, A, Chanro Park, Park, C S, Smith, C, Majhi, P, Hsing-Huang Tseng, Jammy, R, Liu, Tsu-Jae King, Chenming Hu

“…We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special…”
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Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- k/Metal Gate Stacks Directly on SiGe by Huang, J., Kirsch, P.D., Jungwoo Oh, Se Hoon Lee, Majhi, P., Harris, H.R., Gilmer, D.C., Bersuker, G., Dawei Heh, Chang Seo Park, Park, C., Hsing-Huang Tseng, Jammy, R.

“…This letter addresses mechanisms responsible for a high gate leakage current ( Jg ) and a thick interfacial layer in the surface channel SiGe pFET enabling…”
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Origin of the Flatband-Voltage Roll-Off Phenomenon in Metal/High- k Gate Stacks by Bersuker, G, Chang Seo Park, Huang-Chun Wen, Choi, K, Price, J, Lysaght, P, Hsing-Huang Tseng, Sharia, O, Demkov, A, Ryan, J T, Lenahan, P

“…The effect of flatband-voltage reduction [roll-off (R-O)], which limits fabrication options for obtaining the needed band-edge threshold voltage values in…”
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Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates by Jungwoo Oh, Majhi, P., Lee, H., Oooksang Yoo, Banerjee, S., Chang Yong Kang, Ji-Woon Yang, Harris, R., Hsing-Huang Tseng, Jammy, R.

“…The authors report on the novel MOSFETs that were fabricated on thin relaxed Ge epitaxial layers grown on Si substrates. With controlled epi-Ge thickness,…”
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Fermi-level pinning at the polysilicon/metal-oxide interface-Part II by Hobbs, C.C., Fonseca, L.R.C., Knizhnik, A., Dhandapani, V., Samavedam, S.B., Taylor, W.J., Grant, J.M., Dip, L.G., Triyoso, D.H., Hegde, R.I., Gilmer, D.C., Garcia, R., Roan, D., Lovejoy, M.L., Rai, R.S., Hebert, E.A., Hsing-Huang Tseng, Anderson, S.G.H., White, B.E., Tobin, P.J.

“…We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the…”
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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate by Se-Hoon Lee, Majhi, P., Ferrer, D. A., Pui-Yee Hung, Huang, J., Oh, J., Wei-Yip Loh, Sassman, B., Byoung-Gi Min, Hsing-Huang Tseng, Harris, R., Bersuker, G., Kirsch, P. D., Jammy, R., Banerjee, S. K.

“…Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels…”
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A Study of Strain Engineering Using CESL Stressor on Reliability Comparing Effect of Intrinsic Mechanical Stress by Kyong Taek Lee, Chang Yong Kang, Min-Sang Park, Byoung Hun Lee, Ho Kyung Park, Hyun Sang Hwang, Hsing-Huang Tseng, Jammy, R., Yoon-Ha Jeong

“…The effects of a stressor nitride layer on device performance and reliability are investigated. To decouple intrinsic mechanical stress and process-related…”
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Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation by Wei-Yip Loh, Etienne, H., Coss, B., Ok, I., Turnbaugh, D., Spiegel, Y., Torregrosa, F., Banti, J., Roux, L., Pui-Yee Hung, Jungwoo Oh, Sassman, B., Radar, K., Majhi, P., Hsing-Huang Tseng, Jammy, R.

“…Using a presilicide implantation approach, we demonstrate that the Schottky barrier height (SBH) of NiSi/n-Si(100) can be modulated by doping a Si substrate…”
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The Effect of a Si Capping Layer on RF Characteristics of High- k /Metal Gate SiGe Channel pMOSFETs by Min Sang Park, Kyong Taek Lee, Chang Yong Kang, Gil-Bok Choi, Hyun Chul Sagong, Chang Woo Sohn, Byoung-Gi Min, Jungwoo Oh, Majhi, Prashant, Hsing-Huang Tseng, Lee, Jack C, Jeong-Soo Lee, Jammy, Raj, Yoon-Ha Jeong

“…We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices,…”
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Characteristics of Gate Current Random Telegraph Signal Noise in SiON/HfO2/TaN p-Type Metal--Oxide--Semiconductor Field-Effect Transistors under Negative Bias Temperature Instability Stress Condition by Zhang, Liangliang, Liu, Changze, Wang, Runsheng, Huang, Ru, Yu, Tao, Zhuge, Jing, Kirsch, Paul, Tseng, Hsing-Huang, Wang, Yangyuan

“…Gate dielectric traps are becoming a major concern in the high-$k$/metal gate devices. In this paper, new experimental results and in-depth study on gate…”
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Spectroscopic analysis of the process-dependent microstructure of ultra-thin high-k gate dielectric film systems by Lysaght, Patrick S., Bersuker, Gennadi, Tseng, Hsing-Huang, Jammy, Raj

“…HfO2 gate dielectric thin films have been exposed to anneal processing in NH3 and N2 ambient in order to decouple the influence of N incorporation from that of…”
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Gate stack technology for nanoscale devices by Lee, Byoung Hun, Oh, Jungwoo, Tseng, Hsing Huang, Jammy, Rajarao, Huff, Howard

“…Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) of past…”
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Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate by Yoo, Ook Sang, Oh, Jungwoo, Kang, Chang Yong, Lee, Byoung Hun, Han, In Shik, Choi, Won-Ho, Kwon, Hyuk-Min, Na, Min-Ki, Majhi, Prashant, Tseng, Hsing-Huang, Jammy, Raj, Wang, Jin Suk, Lee, Hi-Deok

“…We demonstrated the effect of post-metallization annealing and Si interlayer thickness on Ge MOS capacitor on Ge-on-Si substrate with HfO 2/TaN. Ge…”
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Combined Effects of an Epitaxial Ge Channel and Si Substrate on Ge-on-Si Metal–Oxide–Semiconductor Capacitors and Field Effect Transistors by Oh, Jungwoo, Majhi, Prashant, Lee, Hi-Deok, Banerjee, Sanjay, Harris, Rusty, Tseng, Hsing-Huang, Jammy, Raj

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Fermi-level pinning at the polysilicon/metal oxide interface-Part I by Hobbs, C.C., Fonseca, L.R.C., Knizhnik, A., Dhandapani, V., Samavedam, S.B., Taylor, W.J., Grant, J.M., Dip, L.G., Triyoso, D.H., Hegde, R.I., Gilmer, D.C., Garcia, R., Roan, D., Lovejoy, M.L., Rai, R.S., Hebert, E.A., Hsing-Huang Tseng, Anderson, S.G.H., White, B.E., Tobin, P.J.

“…We report here that Fermi pinning at the polysilicon/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning…”
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Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-k/Metal Gates CMOS FinFETs for Multi-VTh Engineering by MUHAMMAD MUSTAFA HUSSAIN, SMITH, Casey E, RUSTY HARRIS, H, YOUNG, Chadwin D, TSENG, Hsing-Huang, JAMMY, Rajarao

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Effect of substrate hot carrier stress on high-k gate stack by Hokyung Park, Bersuker, G., Chang Yong Kang, Young, C., Hsing-Huang Tseng, Jammy, R.

“…The origin of stress induced leakage current and defect generation process in the high-k/metal gate stacks under the substrate hot carrier stress and constant…”
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Dual work function high-k/Metal Gate CMOS FinFETs by Hussain, M.M., Smith, C., Kalra, P., Ji-Woon Yang, Gebara, G., Sassman, B., Kirsch, P., Majhi, P., Seung-Chul Song, Harris, R., Hsing-Huang Tseng, Jammy, R.

“…For the first time, a set of complementary metal oxide semiconductor (CMOS) FinFET devices with two different high-k/metal gate stacks of dual work function…”
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