Search Results - "Tschanz, J.W."

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance by Bowman, K.A., Tschanz, J.W., Nam Sung Kim, Lee, J.C., Wilkerson, C.B., Lu, S.-L.L., Karnik, T., De, V.K.

“…A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic…”
Get full text

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage by Tschanz, J.W., Kao, J.T., Narendra, S.G., Nair, R., Antoniadis, D.A., Chandrakasan, A.P., De, V.

“…Bidirectional adaptive body bias (ABB) is used to compensate for die-to-die parameter variations by applying an optimum pMOS and nMOS body bias voltage to each…”
Get full text

Dynamic sleep transistor and body bias for active leakage power control of microprocessors by Tschanz, J.W., Narendra, S.G., Ye, Y., Bloechel, B.A., Borkar, S., De, V.

“…In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant…”
Get full text

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors by Tschanz, J.W., Narendra, S., Nair, R., De, V.

“…Adaptive supply voltage as well as adaptive body bias may be used to control the frequency and leakage distribution of fabricated microprocessor dies. Test…”
Get full text

Formal derivation of optimal active shielding for low-power on-chip buses by Ghoneima, M., Ismail, Y.I., Khellah, M.M., Tschanz, J.W., De, V.

“…Passive shielding has been used to reduce the capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between…”
Get full text

Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques by Ghoneima, M., Ismail, Y.I., Khellah, M.M., Tschanz, J.W., De, V.

“…This paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on…”
Get full text

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS by Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Borkar, N.

“…This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This…”
Get full text

Impact of Parameter Variations on Circuits and Microarchitecture by Unsal, O.S., Tschanz, J.W., Bowman, K., De, V., Vera, X., Gonzalez, A., Ergin, O.

“…Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both…”
Get full text

Refueling: Preventing Wire Degradation due to Electromigration by Abella, J., Vera, X., Unsal, O.S., Ergin, O., Gonzalez, A., Tschanz, J.W.

“…Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable…”
Get full text

A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits by Pan, A., Tschanz, J.W., Kundu, S.

“…Aggressive scaling of CMOS transistors in last four decades has resulted in circuits with progressively higher packing density, increased switching speed, and…”
Get full text

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process by Hazucha, P., Karnik, T., Walstra, S., Bloechel, B.A., Tschanz, J.W., Maiz, J., Soumyanath, K., Dermer, G.E., Narendra, S., De, V., Borkar, S.

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
Get full text

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance by Bowman, K.A., Tschanz, J.W., Nam Sung Kim, Lee, J.C., Wilkerson, C.B., Lu, S.-L.L., Karnik, T., De, V.K.

“…Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic…”
Get full text

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS by Vangal, S, Anders, M.A, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J.W, Ye, Y, Somasekhar, D, Bloechel, B.A, Dermer, G.E, Krishnamurthy, R.K, Soumyanath, K, Mathew, S, Narendra, S.G, Stan, M.R, Thompson, S, De, V, Borkar, S

Get full text

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process by Hazucha, P, Karnik, T, Walstra, S, Bloechel, BA, Tschanz, J W, Maiz, J, Soumyanath, K, Dermer, GE, Narendra, S, De, V, Borkar, S

“…We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches…”
Get full text

Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process by HAZUCHA, Peter, KARNIK, Tanay, BORKAR, Shekhar, WALSTRA, Steven, BLOECHEL, Bradley A, TSCHANZ, James W, MAIZ, Jose, SOUMYANATH, Krishnamurthy, DERMER, Gregory E, NARENDRA, Siva, DE, Vivek

Get full text

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS by Vangal, S., Anders, M.A., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Tschanz, J.W., Ye, Y., Somasekhar, D., Bloechel, B.A., Dermer, G.E., Krishnamurthy, R.K., Soumyanath, K., Mathew, S., Narendra, S.G., Stan, M.R., Thompson, S., De, V., Borkar, S.

“…A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry…”
Get full text

Comparative analysis of conventional and statistical design techniques by Burns, Steven M., Ketkar, Mahesh, Menezes, Noel, Bowman, Keith A., Tschanz, James W., De, Vivek

“…We explore the power benefits of changing a microprocessor path histogram through circuit sizing based on statistical timing analysis and optimization (STAO)…”
Get full text

Leakage and process variation effects in current testing on future CMOS circuits by Keshavarzi, A., Tschanz, J.W., Narendra, S., De, V., Daasch, W.R., Roy, K., Sachdev, M., Hawkins, C.F.

“…Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative…”
Get full text