Search Results - "Tsau-Shuan Wu"
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1
Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking
Published in 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (01-09-2008)“…Radiation-induced soft errors on large-scale integrated circuits are becoming increasingly problematic as device sizes are scaled down, operating voltages are…”
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Conference Proceeding
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2
Complexity reduction for analog circuit performance models using random forests
Published in 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC) (01-10-2009)“…Most existing optimization methods for analog circuits focus on the accuracy of their performance modeling techniques, which results in complicated and…”
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Conference Proceeding