Search Results - "Truong, Dean N"

A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders by Mohsenin, Tinoosh, Truong, Dean N, Baas, Bevan M

“…A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout…”
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A 167-Processor Computational Platform in 65 nm CMOS by Truong, D.N., Cheng, W.H., Mohsenin, T., Zhiyi Yu, Jacobson, A.T., Landge, G., Meeuwsen, M.J., Watnik, C., Tran, A.T., Zhibin Xiao, Work, E.W., Webb, J.W., Mejia, P.V., Baas, B.M.

“…A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock…”
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Circuit modeling for practical many-core architecture design exploration by Truong, Dean N, Baas, Bevan M

“…Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the…”
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A complete real-time 802.11a baseband receiver implemented on an array of programmable processors by Tran, A.T., Truong, D.N., Baas, B.M.

“…This paper reports the design and software implementation of a real-time digital baseband receiver compliant with the IEEE 802.11a standard on the AsAP2…”
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The design of a reconfigurable continuous-flow mixed-radix FFT processor by Jacobson, A.T., Truong, D.N., Baas, B.M.

“…The design of a highly configurable continuous flow mixed-radix (CFMR) fast Fourier transform (FFT) processor is presented. It computes fixed-point complex…”
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A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors by Tran, A.T., Truong, D.N., Baas, B.M.

“…The globally asynchronous locally synchronous (GALS) design style for a large area chip has become increasingly attractive due to the difficulty of designing…”
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Massively parallel processor array for mid-/back-end ultrasound signal processing by Truong, D N, Baas, B M

“…Ultrasound remains a popular imaging modality due to its mobility and cost-effectiveness. As general purpose computing and DSPs are entering an era of…”
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A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network by Tran, A.T., Truong, D.N., Baas, B.M.

“…This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets…”
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