Search Results - "Trevisoli, R. D."

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors by Cerdeira, A., Estrada, M., Iniguez, B., Trevisoli, R.D., Doria, R.T., de Souza, M., Pavanello, M.A.

“…•Continuous model for Symmetric Double-Gate Junctionless Transistors is proposed.•The model is physically-based for depletion and accumulation operating…”
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Harmonic distortion analysis of short channel junctionless nanowire transistors operating as amplifiers by Doria, R. T., Trevisoli, R. D., de Souza, M., Pavanello, M. A.

“…This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (junctionless nanowire transistors) of several L. It is shown that, at a…”
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Analog operation of junctionless transistors at cryogenic temperatures by Doria, R T, Pavanello, M A, Trevisoli, R D, de Souza, M, Lee, C W, Ferain, I, Dehdashti Akhavan, N, Yan, R, Razavi, P, Yu, R, Kranti, A, Colinge, J P

“…This work presented the analog behavior of nMOS Junctionless transistors in the temperature range of 100 K to 473 K investigated by experimental results and…”
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Junctionless Multiple-Gate Transistors for Analog Applications by Doria, R. T., Pavanello, M. A., Trevisoli, R. D., de Souza, M., Chi-Woo Lee, Ferain, I., Akhavan, N. D., Ran Yan, Razavi, P., Ran Yu, Kranti, A., Colinge, J.

“…This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited…”
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Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors by Trevisoli, R. D., Doria, R. T., de Souza, M., Das, S., Ferain, I., Pavanello, M. A.

“…This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation…”
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Ultra-low-power diodes using junctionless nanowire transistors by de Souza, M., Doria, R. T., Trevisoli, R. D., Pavanello, M. A.

“…In this work, the performance of Ultra-Low-Power (ULP) Diodes implemented with Junctionless Nanowire Transistors (JNTs) is presented for the first time…”
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Cryogenic Operation of Junctionless Nanowire Transistors by de Souza, M., Pavanello, M. A., Trevisoli, R. D., Doria, R. T., Colinge, J.

“…This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current,…”
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Trap density characterization through low-frequency noise in junctionless transistors by Doria, Rodrigo Trevisoli, Trevisoli, Renan Doria, de Souza, Michelly, Pavanello, Marcelo Antonio

“…[Display omitted] •Current noise spectral density of JNTs with different gate dielectrics is evaluated.•Devices with SiO2 gate dielectric present lower trap…”
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Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors by Doria, R. T., Trevisoli, R. D., de Souza, M., Ferain, I., Das, S., Pavanello, M. A.

“…This work presented an experimental analysis of the LFN in p and n-type JNTs of different L and doping concentrations. JNTs have shown 1/f noise as the main…”
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The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors by Trevisoli, R. D., Doria, R. T., de Souza, M., Ferain, I., Das, S., Pavanello, M. A.

“…This work presented an evaluation of the zero temperature coefficient bias in Junctionless Nanowire Transistors. Contrarily to results of previous works, this…”
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Analysis of the Low-Frequency Noise of Junctionless Nanowire Transistors operating in saturation by Doria, R. T., Trevisoli, R. D., de Souza, M., Colinge, J. P., Pavanello, M. A.

“…This work presented the LF noise behavior of nMOS JNTs investigated by experimental results. It was shown that JNTs can present either 1/f or 1/f 2 noises,…”
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Analytical model for potential in double-gate juntionless transistors by Cerdeira, Antonio, Estrada, Magali, Trevisoli, R. D., Doria, R. T., de Souza, Michelly, Pavanello, Marcelo A.

“…An analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and…”
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Analysis of charges densities in multiple-gates SOI nMOS junctionless by Mariniello, G., Cerdeira, A., Estrada, M., Doria, R. T., Trevisoli, R. D., de Souza, M., Pavanello, M. A.

“…This paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions.. The analysis of the charge densities was done…”
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Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations by Mariniello, G., Doria, R. T., de Souza, M., Pavanello, M. A., Trevisoli, R. D.

“…Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel…”
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Drain current model for junctionless nanowire transistors by Trevisoli, R. D., Doria, R. T., de Souza, M., Pavanello, M. A.

“…Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a…”
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