Search Results - "Trevillyan, L.H."

Global flow optimization in automatic logic design by Berman, C.L., Trevillyan, L.H.

“…A method for optimizing digital logic networks is described. This approach uses the techniques of global flow analysis to efficiently gather information about…”
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The integration of logic synthesis and high-level synthesis by Camposano, R., Trevillyan, L.H.

“…The relationship between high-level synthesis and logic synthesis is investigated and the factors that influence the interface between them are discussed. It…”
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Functional comparison of logic designs for VLSI circuits by Berman, C.L., Trevillyan, L.H.

“…A method is described for circuit equivalence which proceeds by reducing the question of whether two circuits are equivalent to a number of a more easily…”
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Representative traces for processor models with infinite cache by Iyengar, V.S., Trevillyan, L.H., Bose, P.

“…Performance evaluation of processor designs using dynamic instruction traces is a critical part of the iterative design process. The widening gap between the…”
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Efficient techniques for timing correction by Berman, C.L., Hathaway, D.J., LaPaugh, A.S., Trevillyan, L.H.

“…Three computationally efficient methods (frontier motion, Shannon expansion, and Boolean distribution) for restructuring logic which fails to meet timing…”
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Technology Adaptation in Logic Synthesis by Joyner, W.H., Trevillyan, L.H., Brand, D., Nix, T.A., Gundersen, S.C.

“…Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements, from Boolean minimizers to…”
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