Search Results - "Toifl, Thomas"

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer by Morf, Thomas, Klein, Bernhard, Despont, Michel, Drechsler, Ute, Kull, Lukas, Corcos, Dan, Elad, Danny, Kaminski, Noam, Pfeiffer, Ullrich R., Al Hadi, Richard, Keller, Hans M., Braendli, Matthias, Menolfi, Christian, Kossel, Marcel, Francese, Pier Andrea, Toifl, Thomas, Plettemeier, Dirk

“…We report on the design, fabrication and measurements of a new THz sensor concept based on an antenna-coupled MOSFET bolometer for room-temperature passive THz…”
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A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS by Kull, Lukas, Toifl, Thomas, Schmatz, Martin, Francese, Pier Andrea, Menolfi, Christian, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Andersen, Toke Meyer, Leblebici, Yusuf

“…An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of…”
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A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET by Kull, Lukas, Luu, Danny, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas

“…A 24-72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB SNDR at Nyquist…”
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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET by Kim, Gain, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Burg, Andreas, Toifl, Thomas, Leblebici, Yusuf, Kull, Lukas, Luu, Danny, Braendli, Matthias, Menolfi, Christian, Francese, Pier-Andrea, Yueksel, Hazar, Aprile, Cosimo, Morf, Thomas

“…This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX…”
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Integrated circuits for particle physics experiments by Snoeys, W., Anelli, G., Campbell, M., Cantatore, E., Faccio, F., Heijne, E.H.M., Jarron, P., Kloukinas, K.C., Marchioro, A., Moreira, P., Toifl, T., Wyllie, K.

“…High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons,…”
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Session 8 Overview: Ultra-High-Speed Wireline by Frans, Yohan, Yue, Patrick, Toifl, Thomas

“…As data center and telecommunication infrastructure bandwidth requirements continue to increase, networking products with 112Gb/s electrical and optical…”
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Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS by Kull, Lukas, Pliva, Jan, Toifl, Thomas, Schmatz, Martin, Francese, Pier Andrea, Menolfi, Christian, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Andersen, Toke Meyer, Leblebici, Yusuf

“…A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100…”
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A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET by Luu, Danny, Kull, Lukas, Toifl, Thomas, Menolfi, Christian, Brandli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Yueksel, Hazar, Cevrero, Alessandro, Ozkaya, Ilter, Huang, Qiuting

“…A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak…”
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An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels by Aprile, Cosimo, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Braendli, Matthias, Kossel, Marcel, Morf, Thomas, Kull, Lukas, Oezkaya, Ilter, Leblebici, Yusuf, Cevher, Volkan, Toifl, Thomas

“…This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme,…”
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A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery by Andersen, Toke M., Krismer, Florian, Kolar, Johann W., Toifl, Thomas, Menolfi, Christian, Kull, Lukas, Morf, Thomas, Kossel, Marcel, Brandli, Matthias, Francese, Pier Andrea

“…Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future…”
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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET by Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas

“…A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity,…”
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Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters by Andersen, Toke M., Krismer, Florian, Kolar, Johann W., Toifl, Thomas, Menolfi, Christian, Kull, Lukas, Morf, Thomas, Kossel, Marcel, Brandli, Matthias, Francese, Pier Andrea

“…The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip…”
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A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS by Menolfi, Christian, Toifl, Thomas, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Cevrero, Alessandro, Kossel, Marcel, Kull, Lukas, Luu, Danny, Ozkaya, Ilter

“…The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these…”
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A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth by Francese, Pier Andrea, ToifI, Thomas, Buchmann, Peter, Brändli, Matthias, Menolfi, Christian, Kossel, Marcel, Morf, Thomas, Kull, Lukas, Andersen, Toke Meyer

“…A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized…”
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Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders by Yueksel, Hazar, Braendli, Matthias, Burg, Andreas, Cherubini, Giovanni, Cideciyan, Roy D., Francese, Pier Andrea, Furrer, Simeon, Kossel, Marcel, Kull, Lukas, Luu, Danny, Menolfi, Christian, Morf, Thomas, Toifl, Thomas

“…The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power…”
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A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET by Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas

“…This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero…”
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A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology by Bulzacchelli, J. F., Menolfi, C., Beukema, T. J., Storaska, D. W., Hertle, J., Hanson, D. R., Ping-Hsuan Hsieh, Rylov, S. V., Furrer, D., Gardellini, D., Prati, A., Morf, T., Sharma, V., Kelkar, R., Ainspan, H. A., Kelly, W. R., Chieco, L. R., Ritter, G. A., Sorice, J. A., Garlett, J. D., Callan, R., Brandli, M., Buchmann, P., Kossel, M., Toifl, T., Friedman, D. J.

“…This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes…”
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A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS by Reutemann, Robert, Ruegg, Michael, Keyser, Fran, Bergkvist, John, Dreps, Daniel, Toifl, Thomas, Schmatz, Martin

“…This paper describes the design of a product-level low-power source-synchronous link receiver macro for data rates of 3.2-6.4 Gb/s. The receiver macro consists…”
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F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets by Gonzalez, Christopher, Liu, Huichu, Noh, Mijung, Karl, Eric, Toifl, Thomas, Hsu, Shawn

“…Summary form only given, as follows. The end of transistor scaling drives innovative 2.5D, 3D and chiplet technologies to further extend Moore's law. Recent…”
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A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET by Kull, Lukas, Luu, Danny, Menolfi, Christian, Braendli, Matthias, Francese, Pier Andrea, Morf, Thomas, Kossel, Marcel, Cevrero, Alessandro, Ozkaya, Ilter, Toifl, Thomas

“…Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require ADCs with more than 50GS/s and at least 5 ENOB to enable complex…”
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